Dandan Ding

A hardware CABAC encoder for HEVC

This paper presents a hardware design of context-based adaptive binary arithmetic coding (CABAC) for the emerging High efficiency video coding (HEVC) standard. While aiming at higher compression efficiency, the CABAC in HEVC also invests a lot of effort in the pursuit of parallelism and reducing hardware cost. Simulation results show that our design processes 1.18 bins per cycle on average. It can work at 357 MHz with 48.940K gates targeting 0.13 μm CMOS process. This processing rate can support real-time encoding for all sequences under common test conditions of HEVC standard conforming to the main profile level 6.1 of main tier or main profile level 5.1 of high tier.

Video decoder reconfigurations and AVS extensions in the new MPEG reconfigurable video coding framework

Multimedia devices are now required to support multiple coding standards. Supporting seamlessly both interoperability between standards and flexibility for application specific optimizations is a great challenge for current video coding technology. After a brief description of the new MPEG reconfigurable video coding (RVC) framework, this paper describes possible decoder reconfigurations within this framework. The essential idea behind this framework is to reuse as most as possible the algorithms or architectures which are common to several different standards and to reconfigure video decoders in a flexible way at the coding tool level. A coding tool is an encapsulated piece of algorithm. Reconfiguration can address specific optimization objectives such as improvement in colour reproduction or higher performance at high bitrate. These simple examples show that the tool level definition of the video tool library is flexible enough to support the incremental introduction of new coding algorithms, the usage of algorithms taken from different video standards (i.e. AVS is provided in one example), and the possibility of high level reconfigurations. Thus, this paper demonstrates that the RVC framework offers a great flexibility in selecting coding tools for decoder reconfigurations to satisfy a wide variety of different applications.

Reconfigurable video coding framework and decoder reconfiguration instantiation of AVS

In 2004, a new standardization activity called reconfigurable video coding (RVC) was started by MPEG with the purpose of offering a framework which provides reconfiguration capabilities for standard video coding technology. The essential idea of RVC framework is a dynamic dataflow mechanism of constructing new video codecs by a collection of video coding tools from video tool libraries. With this objective, RVC framework is not restricted to specific coding standard, but defined at coding tools level with interoperability to achieve high flexibility and reusability. Three elements are normative in RVC framework: decoder description (DD), video tool library (VTL) and abstract decoder model (ADM). With these elements, a standard or new decoder is able to be reconfigured in RVC framework. This paper presents the procedure of describing a reconfigured decoder in DD, reusing and exchanging tools from VTLs and initializing ADM in the dataflow formalism of RVC framework. A decoder configuration which can be instantiated as AVS intra decoder configuration or other new decoder configurations in RVC framework is described as an example by using coding tools from China audio video coding standard (AVS) and MPEG series. It is shown that the process mechanism offered by RVC framework is versatile and flexible to achieve high reusability and exchangeability in decoder configurations.

A hardware-oriented IME algorithm and its implementation for HEVC

The flexible coding structure in High Efficiency Video Coding (HEVC) introduces many challenges to real-time implementation of the integer-pel motion estimation (IME). In this paper, a hardware-oriented IME algorithm naming parallel clustering tree search (PCTS) is proposed, where various prediction units (PU) are processed simultaneously with a parallel scheme. The PCTS consists of four hierarchical search steps. After each search step, PUs with the same MV candidate are clustered to one group. And the next search step is shared by PUs in the same group. Owing to the top-down tree-structure search strategy of the PCTS, search processes are highly shared among different PUs and system throughput is thus significantly increased. As a result, the hardware implementation based on the proposed algorithm can support real-time video applications of QFHD (3840×2160) at 30fps.

A cost-efficient hardware architecture of deblocking filter in HEVC

This paper presents a hardware architecture of deblocking filter (DBF) for High Efficiency Video Coding (HEVC) by jointly considering system throughput and hardware cost. A hybrid pipeline with two processing levels is adopted to improve system performance. With the hybrid pipeline, only one 1-D filter and single-port on-chip SRAM are used. According to the data dependence between neighbouring edges, a shifted 16×16 basic processing unit as well as corresponding filtering order is proposed. It reduces memory cost and makes the DBF friendlier to work in a coding/decoding system. The proposed hardware architecture is synthesized under 0.13um standard CMOS technology and result shows that it consumes 17.6k gates at an operating frequency of 250MHz. Consequently, the design can support real-time processing of QFHD (3840×2160) video applications at 60 fps.

Efficient data flow variable length decoding implementation for the MPEG reconfigurable video coding framework

In 2004, ISO/IEC SC29 better known as MPEG started a new standard initiative aiming at facilitating the deployment of multi-format video codec design and to enable the possibility of reconfiguring video codecs using a library of standard components. The new standard under development is called MPEG Reconfigurable Video Coding (RVC) framework. Whereas video coding tools are specified in the RVC library, when a new decoder is reconfigured choosing in principle any (sub)-set of tools, the corresponding bitstream syntax, described using MPEG-21 BSDL schema, and the associated parser need to be respectively derived and instantiated reconfiguration by reconfiguration. Therefore, the development of an efficient systematic procedure able to instantiate efficient bitstream parsing and particularly variable length decoding is an important component in RVC. This paper introduces an efficient data flow based implementation of the variable length decoding (VLD) process particularly adapted for the instantiation and synthesis of CAL parsers in the MPEG RVC framework.

Memory bandwidth efficient hardware architecture for AVS encoder

A memory bandwidth efficient architecture for AVS encoder is proposed in this paper. First, simplified ME (motion estimation) algorithms are designed to reduce the memory and bandwidth cost. Then a data reuse method with simple control mechanism is proposed to increase the utilization of on-chip memory. The proposed architecture efficiently reduces the bandwidth and memory consumption with acceptable degradation in coding performance. The encoder is implemented with 640 K logic gates in 0.18 mu m2 CMOS technology and can satisfy real time encoding of 720 times576 4:2:0 25 fps AVS video at the working frequency of 108 MHz.

1/2 and 1/4 pixel paralleled FME with a scalable search pattern for HEVC ultra-HD encoding

A hardware design of fractional motion estimation (FME) for high-efficiency video coding (HEVC) is presented in this paper. To achieve one-iteration search and adapt to different applications, several search patterns are evaluated by a trade-off between coding efficiency and computational complexity and finally a scalable search pattern is formed. Based on the scalable search pattern, a search order is elaborately designed for 1/2 and 1/4 pixel paralleled interpolation, with which system throughput is significantly improved. Results show that with 200MHz working frequency, the proposed design is able to process Ultra-HD(3840×2160) videos@30~60fps in real time with full partition depths and modes of HEVC supported.

Transform coding in AVS2

This paper describes the transform coding in the second generation of Audio-video Coding Standard (AVS2). In AVS2, 16-bit integer DCT transform scheme is adopted, with the transform block size varies from 4×4 to 32×32, and the smaller transform kernels are completely embedded in the larger ones. To keep strong decorrelation capability of the transform, a principle is proposed in this paper to design the transform kernel by jointly minimizing DCT distortion, orthogonality and normalization. Furthermore, complexity of the transform is analyzed based on the proposed hybrid butterfly architecture, in which the transform is decomposed into a butterfly structure and a low-cost matrix multiplication. Experiment result shows that 25.7% additions and 71.0% shift operations can be saved by using this architecture compared with the partial butterfly one.

A reconfiguration system for video decoder

This demonstration system shows a kind of video decoders implementation in Reconfigurable Video Coding (RVC) framework on Open RVC-CAL Compiler (Orcc) platform. Differently from tradition video decoder, the reconfigurable video decoder is not a decoder conforming a special video coding standard, but dynamically built according to actual bitsteams, which may not conform any standard. The reconfigurable video decoder receives not only the compressed video bitstream but also the decoder description. As an example, in this demo, we reconfigure AVS and H.264/AVC decoders using Just-In-Time Adaptive Decoder Engine (Jade).