Daniel C. Dinis
University of Aveiro
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Publication
Featured researches published by Daniel C. Dinis.
digital systems design | 2015
Diogo Riscado; Jorge Santos; Daniel C. Dinis; Gustavo Anjos; Daniel Belo; Nuno Borges Carvalho; Arnaldo S. R. Oliveira
This paper presents a laboratorial platform for the development and trial of C-RAN compliant features. As part of future mobile networks standardization, C-RAN is considered as an evolution of the current RAN, which inherent challenges represent an interesting topic of research among academic institutions and industry. The proposed testbed is intended to provide a cost-effective emulation of the high price and vendor-specific closed radio base station equipment such as BBU and RRH modules. Based on open FPGA platforms, it leads to a high level of flexibility according to user-defined configurations as well as it provides a high set of real-world deployments features, such as the optical CPRI interface, multi-mode and multi-band capabilities. Furthermore, due to its modularity it is targeted for a wide range of C-RAN applications and optimization scenarios such as CoMP, cloud processing and baseband signal compression.
international microwave symposium | 2016
Daniel C. Dinis; Rui Fiel Cordeiro; Arnaldo S. R. Oliveira; José M. N. Vieira
Fully digital transmitters have been thoroughly explored over the last few years to develop a novel type of agile, reconfigurable, multi-band, multi-standard and highly-efficient transmitters. However, with regard to agility and reconfigurability, current state-of-the-art approaches are still very restrictive. This paper proposes a new architecture based on a tunable delta-sigma modulator suitable for designing RF fully digital transmitters either in single-carrier or in dual-carrier scenarios. A 2-path polyphase decomposition was also developed to optimize some figures of merit, such as SNR and EVM, and to demonstrate the scalability of this type of modulator. This novel architecture has been successfully implemented and validated on an FPGA-based transmitter for single- and dual-carrier scenarios.
IEEE Transactions on Microwave Theory and Techniques | 2016
Daniel C. Dinis; Rui Fiel Cordeiro; Filipe M. Barradas; Arnaldo S. R. Oliveira; José M. N. Vieira
In this paper, a new architecture for designing tunable single- and dual-band radio-frequency fully digital transmitters is proposed and validated. The proposed architecture excels the state of the art in terms of simplicity and flexibility. While its short critical path leverages the use of equivalent polyphase decomposition techniques to increase the global systems sampling frequency, the capability of changing the systems frequency response in real time enables its use in both single- and dual-band transmission scenarios. To mitigate a crosstalk in the dual-band scenario, a precompensation technique is also proposed. This novel concept has been successfully validated in a field-programmable gate array (FPGA) based transmitter. To validate both the proposed transmitter as well as the precompensation mechanism, spectrum and error-vector magnitude (EVM) measurements were obtained for two scenarios with a carrier frequency of 2.5 GHz: 1) single-band, using quadrature phase-shifting keying (QPSK), 16-quadrature amplitude modulation (QAM) and 64-QAM, with no intermediate frequency (IF), for different symbol rate (SR) values (from 3.125 up to 15.625 Msps) and 2) single- and dual-band, using QPSK and 16-QAM, with an SR of 3.125 Msps, for different IF values (from 2 up to 120 MHz). All the experimental results present EVM values below 2.6%, resulting in a well-defined constellation.
IEEE Transactions on Microwave Theory and Techniques | 2018
Daniel C. Dinis; Rui Fiel Cordeiro; Arnaldo S. R. Oliveira; José M. N. Vieira; Tomás Oliveira e Silva
Real-time frequency agility is one of the key limitations of current all-digital transmitters (ADTs). In this paper, to address this problem, an ADT based on direct-RF generation is proposed and implemented in a field-programmable gate array (FPGA). To achieve this, the pulse encoding is performed after the digital upconversion, which presents challenges in the pulse encoder implementation. However, the proposed design considerably improves the frequency agility when compared with current state-of-the-art approaches. Two different pulse encoders were designed in this paper, one is based on pulsewidth modulation (PWM) and the other on delta–sigma modulation (
international midwest symposium on circuits and systems | 2017
Daniel C. Dinis; Rui Fiel Cordeiro; Arnaldo S. R. Oliveira; José M. N. Vieira; Tomás Oliveira e Silva
\mathrm {\Delta \Sigma }\text{M}
international microwave symposium | 2017
Daniel C. Dinis; Nuno Borges Carvalho; Arnaldo S. R. Oliveira; José M. N. Vieira
). These units are implemented with high parallelization to achieve the required equivalent sampling rates. The proposed design enables the implementation of all-digital RF transmitters in FPGA with a widely tunable carrier frequency. In this paper, a variation from 0.1 up to 6 GHz of carrier frequency, with a maximum frequency resolution of 1.5625 MHz, is demonstrated. Measurement results in terms of signal-to-noise ratio (SNR) and error-vector magnitude are presented and discussed. In the case of the PWM, maximum SNRs of 39 and 36 dB were obtained for a 5 and 10 MBd of symbol rates (SRs). In the case of
international microwave symposium | 2017
Daniel C. Dinis; Arnaldo S. R. Oliveira; José M. N. Vieira
\mathrm {\Delta \Sigma }\text{M}
international microwave symposium | 2017
Daniel C. Dinis; Arnaldo S. R. Oliveira; José M. N. Vieira
, maximum SNRs of 38 and 35 dB were obtained for 20 and 40 MBd of the SR.
international conference on electronics, circuits, and systems | 2016
Andre Prata; Rui Fiel Cordeiro; Daniel C. Dinis; Arnaldo S. R. Oliveira; José M. N. Vieira; Nuno Borges Carvalho
In this paper it will be shown that propagating specific state registers in a fully parallel Delta-Sigma Architecture can have a profound impact in enhancing the performance of these type of modulators without stringent requirements in terms of latency and resources usage. An FPGA-based transmitter was implemented and designed to validate the proposed architecture, and to demonstrate that flexible, high-speed and wideband modulators can be implemented with low-complexity and with a low resources usage.
field programmable logic and applications | 2016
Daniel C. Dinis; Rui Fiel Cordeiro; Arnaldo S. R. Oliveira; José M. N. Vieira
This paper discusses the implementation of a solution to study over the air 5G Massive MIMO antenna transmitter arrays. The proposal is based on a multi-sine approach similar to what is being done to explore nonlinear devices. The approach followed is supported on a multi-sine waveform where each element on the array is excited by two tones, being one the common local oscillator, and the other a modulation with a single sinusoid (called a tickle tone). Since each element in the antenna is fed by a different modulated waveform, the overall structure can be evaluated remotely using a simple probe followed by a Vector Signal Analyser. By measuring each of the sines in the receiver stage, the change in amplitude and phase can give an initial approach to each of the transmitter element. The implementation of this solution will be discussed throughout this paper.