Daniel C. Edelstein

Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology

We present the first fully integrated ULSI CMOS/copper interconnect technology. Up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a polycontacted pitch of 0.81 /spl mu/m, on a fully-scaled sub 0.25 /spl mu/m, 1.8 V CMOS technology. The Cu wiring has advantages of significantly lower resistance, higher allowed current density, and increased scalability, relative to comparable Ti/Al(Cu) wiring. These benefits in turn have enabled the scaling of pitch and thickness, from reduced-capacitance, high-density lower levels to low RC global wiring levels, consistent with high-performance and high-density needs. The integrated Cu hardware was evaluated according to a comprehensive set of yield, reliability, and stress tests. This included fully functional, high-density 288 K SRAM chips which were packaged into product modules and successfully tested for reliability. Overall, we find the results for full Cu wiring meet or exceed the standards set by our Al(Cu)/W-stud technology.

RF circuit design aspects of spiral inductors on silicon

In this experiment, the substrate silicon is removed using micromachining techniques, and the remaining thin-film structure is bonded onto a quartz substrate. The micromachined inductor has Q/sub MAX//spl ap/60 at 6 GHz. The lower resistivity and the greater conductor thickness of copper (Cu) compared to the aluminum (Al) process leads to a 3-4/spl times/ increased Q/sub MAX/ over the entire range of feasible inductance values.

VLSI on-chip interconnection performance simulations and measurements

We examine electrical performance issues associated with advanced VLSI semiconductor on-chip interconnections or “interconnects.” Performance can be affected by wiring geometry, materials, and processing details, as well as by processor-level needs. Simulations and measurements are used to study details of interconnect and insulator electrical properties, pulse propagation, and CPU cycle-time estimation, with particular attention to potential advantages of advanced materials and processes for wiring of high-performance CMOS microprocessors. Detailed performance improvements are presented for migration to copper wiring, low-e dielectrics, and scaled-up interconnects on the final levels for long-line signal propagation.

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0

Monolithic spiral inductors fabricated using a VLSI Cu-damascene interconnect technology and low-loss substrates

This paper presents spiral inductor structures optimized in a Cu-damascene VLSI interconnect technology with use of silicon, high-resistivity silicon (HRS), or sapphire substrates. Quality factors (Q) of 40 at 5.8 GHz for a 1.4 nH-inductor and 13 at 600 MHz for a 80 nH-inductor have been achieved.

A high performance liner for copper damascene interconnects

We describe a liner for Cu-Damascene multilevel ULSI interconnects, which satisfies all the important requirements for a high performance and reliable Cu interconnect technology. This liner is implemented in the first manufacturing process to produce and ship CMOS chips with Cu interconnects. The liner is a bilayer from a family of hcp/bcc-TaN followed by bcc-Ta (/spl alpha/-Ta), deposited sequentially in a single PVD chamber from a pure Ta target, using Ar and N/sub 2/ sputtering gases. This bilayer simultaneously maximizes adhesion to the interlevel dielectric and the Cu fill, and has very low in-plane resistivity (/spl sim/30-60 /spl mu//spl Omega/-cm, depending on TaN/Ta thicknesses). These qualities produce high-yield, highly reliable, and electromigration-redundant Cu interconnects.

Characterization of “Ultrathin-Cu”/Ru(Ta)/TaN Liner Stack for Copper Interconnects

Barrier property, gap-fill quality, and electromigration (EM) resistance of a TaN diffusion barrier with ultrathin-Cu/Ru(Ta) liner layers were carried out to evaluate its feasibility for back-end-of-the-line Cu/low- k interconnects. Ru/TaN and Ru0.9 Ta0.1/TaN liner stacks show comparable oxidation and Cu diffusion barrier properties to the conventional Ta/TaN bilayer liner stack. Through observed better wettability to ultrathin Cu seed and therefore enhanced gap-fill quality, both Ru/TaN and Ru0.9 Ta0.1/TaN liner stacks show EM resistance improvement over the Ta/TaN bilayer liner system.

Spiral and solenoidal inductor structures on silicon using Cu-damascene interconnects

Spiral, multilevel spiral, and lateral solenoidal inductor structures are fabricated on silicon substrates using a Cu-damascene VLSI interconnect technology with a 4 /spl mu/m-thick Cu top layer. Some chips are mounted on quartz substrates to suppress substrate losses. An 80-nH, 16-turn spiral inductor on quartz has a Q of 20, the highest recorded value to date for an integrated inductor of this size.

Electromigration in Cu(Al) and Cu(Mn) damascene lines

The effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated. The addition of Mn or Al solute caused a reduction in diffusivity at the Cu/dielectric cap interface and the EM activation energies for both Cu-alloys were found to increase by about 0.2 eV as compared to pure Cu. Mn mitigated and Al enhanced Cu grain boundary diffusion; however, no significant mitigation in Cu grain boundary diffusion was observed in low Mn concentration samples. The activation energies for Cu grain boundary diffusion were found to be 0.74 ± 0.05 eV and 0.77 ± 0.05 eV for 1.5 μm wide polycrystalline lines with pure Cu and Cu (0.5 at. % Mn) seeds, respectively. The effective charge number in Cu grain boundaries Z*GB was estimated from drift velocity and was found to be about −0.4. A significant enhancement in EM lifetimes for Cu(Al) or low Mn concentration bamboo-polycrystalline and near-bamboo grain structures was observed but not for polycrystalline-only alloy lines. These results indicated that the existence of bamboo grains in bamboo-polycrystalline lines played a critical role in slowing down the EM-induced void growth rate. The bamboo grains act as Cu diffusion blocking boundaries for grain boundary mass flow, thus generating a mechanical stress-induced back flow counterbalancing the EM force, which is the equality known as the “Blech short length effect.”The effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated. The addition of Mn or Al solute caused a reduction in diffusivity at the Cu/dielectric cap interface and the EM activation energies for both Cu-alloys were found to increase by about 0.2 eV as compared to pure Cu. Mn mitigated and Al enhanced Cu grain boundary diffusion; however, no significant mitigation in Cu grain boundary diffusion was observed in low Mn concentration samples. The activation energies for Cu grain boundary diffusion were found to be 0.74 ± 0.05 eV and 0.77 ± 0.05 eV for 1.5 μm wide polycrystalline lines with pure Cu and Cu (0.5 at. % Mn) seeds, respectively. The effective charge number in Cu grain boundaries Z*GB was estimated from drift velocity and was found to be about −0.4. A significant enhancement in EM lifetimes for Cu(Al) or low Mn concentration bamboo-polycrystalline and near-bamboo grain structures was observed but not for polycrystalline-only al...

Interface engineering for high interfacial strength between SiCOH and porous SiCOH interconnect dielectrics and diffusion caps

The integration of low- and ultralow-k SiCOH dielectrics in the interconnect structures of very large scale integrated chips involves complex stacks with multiple interfaces. Successful fabrication of reliable chips requires strong adhesion between the different layers of the stacks. A critical interface in the dielectric stack is the interface between the SiCNH diffusion cap and the SiCOH inter- and intralevel dielectrics (ILDs). It was observed that, due to the original deposition conditions, the interface layer was weakened both by a low adhesion strength between SiCNH and SiCOH and by the formation of an initial layer of SiCOH with reduced cohesive strength. The manufacturing process has been modified to engineer this interface and obtain interfacial strengths close to the cohesive strengths of the bulk ILDs. This paper discusses the causes for the original low interfacial strength and presents an approach for enhancing it by engineering the interface to the cap for both the dense SiCOH and porous SiC...