Daniel E. Grupp

Fermi-level depinning for low-barrier Schottky source/drain transistors

By imposing an ultrathin insulator between low-work function metals and silicon, the Schottky barrier of the junction can be substantially reduced, decreasing junction resistance. With this approach, low-Schottky-barrier metal source/drain (S/D) transistors with Mg and Yb as S/D metals are demonstrated.

A new route to zero-barrier metal source/drain MOSFETs

A new method for dramatically lowering the Schottky barrier resistance at a metal/Si interface by interposing an ultrathin insulator is demonstrated for the first time, with thermionic barriers less than those reported to date with silicides. Results with Er and near-monolayer thermal SiN/sub x/ at the interface are consistent with simulations of effective metal Fermi level separations from the silicon conduction band of 0.15 V for n-type Si and 45 mV for p-type Si. Simulations of advanced metal source/drain (S/D) ultrathin-body CMOS devices in comparison with competitive doped S/D devices show a significant performance advantage with a barrier to the conduction band of up to 0.1 V.

Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

For the first time, mixed mode simulation is used to optimize the design of ultrathin-body dual-gate metal source/drain 25-nm CMOS, showing an advantage for source/drain-to-gate underlap, rather than overlap. The effect of source/drain workfunction and silicon thickness on the optimal underlap, and on the resulting circuit speed, is examined. A substantial performance advantage versus doped source/drain is demonstrated.

Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS

Here, for the first time, advanced simulation models are used to investigate the performance advantage of Schottky source/drain ultrathin-silicon technologies at a 25-nm gate length target. Schottky and doped source/drain MOSFETs were optimized and compared using a novel benchmark. Mixed-mode simulations of optimized devices in a two-stage NAND chain show an approximate 45% speed advantage of Schottky source/drain for one set of parameter choices. Contact requirements for Schottky source/drain, and for doped source/drain relative to ITRS targets through 2016, are discussed.