Daniel F. Baldwin

Novel approach to fabricate porous sponges of poly(d,l-lactic-co-glycolic acid) without the use of organic solvents

A novel method was developed to produce highly porous sponges for potential use in tissue engineering, without the use of organic solvents. Highly porous sponges of biodegradable polymers are frequently utilized in tissue engineering both to transplant cells or growth factors, and to serve as a template for tissue regeneration. The processes utilized to fabricate sponges typically use organic solvents, but organic residues remaining in the sponges may be harmful to adherent cells, protein growth factors or nearby tissues. This report describes a technique to fabricate macroporous sponges from synthetic biodegradable polymers using high pressure carbon dioxide processing at room temperature. Solid discs of poly (D,L-lactic-co-glycolic acid) were saturated with CO2 by exposure to high pressure CO2 gas (5.5 MPa) for 72 h at room temperature. The solubility of the gas in the polymer was then rapidly decreased by reducing the CO2 gas pressure to atmospheric levels. This created a thermodynamic instability for the CO2 dissolved in the polymer discs, and resulted in the nucleation and growth of gas cells within the polymer matrix. Polymer sponges with large pores (approximately 100 microns) and porosities of up to 93% could be fabricated with this technique. The porosity of the sponges could be controlled by the perform production technique, and mixing crystalline and amorphous polymers. Fibre-reinforced foams could also be produced by placing polymer fibres within the polymer matrix before CO2 gas processing.

The Role of Gas Dissolution and Induced Crystallization During Microcellular Polymer Processing: A Study of Poly (Ethylene Terephthalate) and Carbon Dioxide Systems

One of the critical steps in the production of microcellular polymers is the dissolution of gas into a polymer matrix. In this paper, the formation of a gas and semicrystalline thermoplastic solution is studied in the presence of a crystallizing matrix with particular emphasis on the ultimate effects of crystallinity on microcellular polymer processing. In this particular study, carbon dioxide was selected as the gas and poly(ethylene terephthalate) (PET) as the polymer. Polymer/gas solution formation is the precursor to the microvoid nucleation and growth during microcellular polymer processing. In batch processing, the solution formation is typically accomplished by placing a polymer sample in a high pressure gas environment resulting in the diffusion of gas into the polymer matrix. For gas and semi-crystalline thermoplastic systems, the solution formation process is notably more complex. In particular, PET crystallizes in the presence of high CO 2 solution concentrations. The crystallization results in a solution that is relatively difficult to microcellular process, requiring relatively high temperatures as compared to amorphous polymer/gas solutions. However, the resulting crystalline foam has a superior microcellular morphology. In addition, the crystallization of the solution results in a lower solubility, an increased matrix stiffness, and a lower diffusivity. Our analysis includes (1) an experimental characterization of the carbon dioxide-induced crystallization occurring during microcellular polymer processing, indicating a critical gas concentration is required for crystallization, (2) an experimental estimation of the viscoelastic belravior of amorphous and semi-crystalline PET/CO 2 solutions, and (3) an experimental investigation of the effects of crystallinity on microcellular processing and the resulting cell morphology. Crystallinity was found to play a major role in microcellular processing through its effects an (a) cell nucleation mechanisms resulting in larger cell densities due to heterogeneous nucleation at the amorphous/crystalline boundaries and (b) cell growth mechanisms resulting in smaller cell sizes due to the increased matrix stiffness of the semi-crystalline matrix

Adhesion mechanisms of nanoparticle silver to substrate materials: identification

Nanoparticle silver (NPS) conductors are increasingly being investigated for printed electronics applications. However, the adhesion mechanism of the nanoparticle silver to substrate materials has not been identified yet. In particular, the adhesion of NPS to organic materials such as the widely used polyimide Kapton HN and Kapton FPC dry films is concerned with low adhesion strength because the processed polymer surface is chemically inert. Moreover, its adhesion to substrate materials such as benzocyclobutene (BCB), copper and aluminum was found to be very weak. Therefore, in this paper, the mechanisms of NPS adhesion to organic and inorganic materials are identified as the first step in improving NPS adhesion strength. Improving the adhesion strength of NPS will be the key issue for printed electronics applications. The adhesion of NPS to substrate materials was found to be mainly attributed to van der Waals forces based on particle adhesion mechanisms. This finding provides the initiative of developing an adhesion prediction model of NPS to substrate materials in order to provide guidelines for improving the NPS adhesion strength to the substrate materials used in printed electronics.

High density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging

A novel micro-electromechanical system (MEMS) package has been developed based on modular, reconfigurable components such as substrate, cap, bond region and through-wafer electrical interconnect (TWEI). The paper presents the details of the process for the fabrication of high density, high aspect ratio TWEIs that includes deep dry etching holes through the substrate, depositing an insulation layer and depositing a conductive layer. Two different processes to make the TWEI have been developed: Post-Process where the TWEI is fabricated after the fabrication of MEMS devices and Pre-Process where the TWEI is fabricated before the fabrication of MEMS device. For both processes, the interconnect holes are created by an anisotropic etching process-inductively coupled plasma (ICP) etching. For the post-process, a silicon dioxide layer was deposited in a plasma enhanced chemical vapor deposition (PECVD) chamber to insulate the interconnect holes. For the pre-process, the PECVD process was replaced with a thermal oxide growth step to ensure a more conformal oxide coating. Three different ways to deposit a conductive layer after deposition of an insulation layer have been practiced: sputtering Cu, electroplating Cu and low-pressure chemical vapor deposition (LPCVD) of phosphorus doped polysilicon. The electrical performance of the TWEIs achieved in each way was measured, analyzed and discussed.

Characterization of a no-flow underfill encapsulant during the solder reflow process

A challenge in flip-chip technology development is to improve the thermo-mechanical reliability of the flip-chip assembly. To increase reliability, an underfill encapsulant is applied to the gap between IC chip and substrate to provide thermal-mechanical protection as well as environmental protection to the assembly. Two processes for applying the underfill encapsulant to the gap between IC chip and substrate can be described as the fast-flow method and the no-flow (reflowable underfill) method. The fast-flow method is currently the most widely used method. The no-flow method is a new innovative method that provides cost savings. In order to develop novel underfill encapsulants for the no-flow process, a better understanding of the underfill properties during the solder reflow is needed. This paper studies two aspects of the No-Flow underfill: fluxing activity and viscosity during reflow. These two aspects are important for proper interconnect formation. Solder wetting studies were conducted by applying the no-flow underfill on top of solder beads on substrates of different metallizations. The samples were then placed in a 7-zone reflow oven on different eutectic type heating cycles. Cross sections of the samples were taken and the angle the solder makes with the substrate was determined. The viscosity of the underfill during reflow is important to allow proper solder interconnects. To acquire the viscosity of the underfill just before, during, and shortly after the solder reflow temperature, a no-flow underfill encapsulant developed at the Georgia Institute of Technology was studied. Samples of this underfill were placed in a 5-zone reflow oven on a standard eutectic cycle and taken out at different points. The samples were then analyzed by differential scanning calorimetry (DSC) to find the % conversion (amount of cure) of the underfill material. These % conversions were then used to find the complex viscosity at different points in the reflow process. In this paper, we present the experimental procedures and results of the No-Flow underfills fluxing abilities and viscosity during reflow heating conditions.

Correlation of flip chip underfill process parameters and material properties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing.

In process stress analysis of flip-chip assemblies during underfill cure

Abstract Low cost flip chip on board assemblies are analyzed during the underfill cure process to determine residual stress generation. In situ stress measurements are performed over the active face of the die during processing and relative in-plane stresses are measured. Experimental measurements are made using flip-chip test vehicles, based on the Sandia National Laboratories’ ATC04 assembly test chip. Four different commercial underfill materials have been evaluated and a relative comparison is presented with respect to the residual stresses produced by each underfill on the flip-chip assemblies. Significant stress variations are observed between the four underfills studied. Correlation between the glass transition temperature ( T g ) and storage modulus ( G ′ ) are made relative to residual stresses produced during underfill cure. Stress relaxation characteristics are also evaluated for the low cost flip-chip assemblies.

High throughput flip chip processing and reliability analysis using no-flow underfills

As a concept to achieve high throughput low cost flip chip on board (FCOB) assembly, a process development activity is underway, implementing next generation flip chip processing based on large area underfill printing/dispensing, integrated chip placement and underfill flow, and simultaneous solder interconnect reflow and underfill cure. Reported in this work is the assembly of a series of test vehicles to assess process yield, process defects, and the reliability of no-flow underfill materials. Critical process design models are presented to predict chip motion during and after the chip placement process, enabling design of the placement process and underfill volume/mass to ensure high yields. Also reported are the results of reliability testing based on air to air and liquid to liquid thermal cycling.

Reliability assessment of microvias in HDI printed circuit boards

Accelerating adoption of CSP and flip-chip area array packaging for high performance and hand-held applications is the main driving force for high-density substrates and printed circuit boards. At the Packaging Research Center, Georgia Institute of Technology (PRC-GT), ultra-fine line high density interconnect (HDI) substrate technology is being developed as part of the system-on-a-package (SOP) research and testbed efforts to meet these emerging requirements. To be adopted by industry, this novel technology must demonstrate the critical elements of high reliability and low cost processing. The HDI and microvias structures discussed in this paper were fabricated on high Tg organic substrates using a sequential build-up process, and were subject to extensive liquid to liquid thermal shock testing. All 75 /spl mu/m microvias and above successfully passed 2000 cycles without failure, and first failure occurred at 1000 cycles for 50 /spl mu/m microvias on a 50 /spl mu/m thick dielectric layer. Microvia down to 25 /spl mu/m diameter on a 25 /spl mu/m thick dielectric layer have passed 2000 cycles with zero failures. Cross-sectioning confirmed that failures were caused by process related defects, such as thin electrolytic copper plating. This paper will discuss the reliability results of the PRC HDI microvias process and methods to improve the mechanical reliability of small photo defined microvias fabricated on similar laminate substrates.

Flip chip interconnect systems using copper wire stud bump and lead free solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly.