Daniel Fischer

Material contrast based inline metrology: process verification and control using back scattered electron imaging on CD-SEM

The Critical Dimension Scanning Electron Microscope (CDSEM) is the traditional workhorse solution for inline process control. Measurements are extracted from top-down images based on secondary electron collection while scanning the specimen. Secondary electrons holding majority of detection yield. These images provide more on the structural information of the specimen surface and less in terms of material contrast. In some cases there is too much structural information in the image which can irritate the measurement, in other cases small but important differences between various material compounds cannot be detected as images are limited by contrast information and resolution of primary scanning beam. Furthermore, accuracy in secondary electron based metrology is limited by charging. To gather the exact required information for certain material compound as needed, a technique, known from material analytic SEM´s has been introduced for inline CDSEM analysis and process control: Low Loss Back Scattered Electron Imaging (LL-BSE). The key at LL-BSE imaging is the collection of only the back scattered electrons (BSE) from outermost specimen surface which undergo the least amount possible of energy loss in the process of image generation following impact of the material by a primary beam. In LL-BSE very good and measurable material distinction and sensitivity, even for very low density material compounds can be achieved. This paper presents new methods for faster process development cycle, at reduced cost, based on LL-BSE mass data mining instead of sending wafers for destructive material analysis.

Electrical property improvements of ultra low-k ILD using a silylation process feasible for process integration.

In this paper the effect of a vapor phase based silylation process on patterned test structures using ULK based ILDs was investigated. It was found that the resistance to capacitance (RC) behavior can be improved. This improvement was found to be scalable, meaning with decreasing metal pitch the RC improvement increases. The silylation process provides in addition a decrease of the leakage current and was found to have adequate defectivity. As the process is feasible for production and the improvement of the electrical properties increases with smaller feature size, it can be assumed that extra costs of the restoration process will be paid out for future technology nodes, if ULK as an ILD is used.

Influence of the process-induced asymmetry on the accuracy of overlay measurements

In the current paper we are addressing three questions relevant for accuracy: 1. Which target design has the best performance and depicts the behavior of the actual device? 2. Which metrology signal characteristics could help to distinguish between the target asymmetry related overlay shift and the real process related shift? 3. How does uncompensated asymmetry of the reference layer target, generated during after-litho processes, affect the propagation of overlay error through different layers? We are presenting the correlation between simulation data based on the optical properties of the measured stack and KLA-Tencor’s Archer overlay measurements on a 28nm product through several critical layers for those accuracy aspects.

Practical aspects of TMU based analysis for scatterometry model referencing

We discuss utilization of TMU (Total Measurement Uncertainty) analysis based on Mandel Regression for scatterometry model referencing. We demonstrate practical instances where the reference metrology uncertainty seems to exceed that of the scatterometry model which, in turn, forces the TMU analysis into an invalid regime. Knowing that the source of this result is the wrong estimation of the reference uncertainty, we focus on reducing the error of the reference metrology as well as improving the reference uncertainty estimation. We are looking at practical aspects of reference metrology hardware and recipes as well as the whole reference metrology setup. We discuss in detail CD-SEM and AFM metrology, as well as other means used to qualify OCD (Optical Critical Dimension) models in a production environment.

Combined process window monitoring for critical features

After critical lithography steps, overlay and CD are measured to determine if the wafers need to be re-worked. Traditionally, overlay metrics are applied per X/Y-direction and, a CD metric is computed independently. From design standpoint, electrical failure is based on a complex interaction between CD deviations and overlay errors. We propose a method including design constraints, where results of different measurement steps are not judged individually, but in a combined way. We illustrate this with a critical design feature consisting of a contact requiring minimum distance to a neighboring metal line, resulting in much better correlation to yield than traditional methods.

Backside defect printability for contact layer with different reticle blank material

Backside defects are out of focus during wafer exposure by the mask thickness and cannot be directly imaged on wafer. However, backside defects will induce transmission variation during wafer exposure. When the size of backside defect is larger than 200 microns, the shadow of such particles will locally change the illumination conditions of the mask patterns and may result in a long range critical dimension (CD) variation on wafer depending on numerical aperture (NA) and pupil shape. Backside defects will affect both wafer CD and critical dimension uniformity (CDU), especially for two-dimensional (2D) structures. This paper focuses on the printability of backside defects on contact layer using annular and quadrupole illumination mode, as well as using different reticle blank material. It also targets for gaining better understanding of critical sizes of backside defects on contact layer for different reticle blanks. We have designed and manufactured two test reticles with repeating patterns of 28nm and 40nm technology node of contact layers. Programmed chrome defects of varying size are placed on the backside opposite to the repeating front side patterns in order to measure the spatial variation of transmission and wafer CD. The test mask was printed on a bare silicon wafer, and the printed features measured for size by spatial sampling. We have investigated two contact layers with different illumination conditions. One is advance binary with single exposure; another is phase shift mask with double exposure. Wafer CD variation for different backside defect sizes are demonstrated for the two contact layers. The comparison between backside defect size with inter-field and intra-field CD variation is also discussed.