Daniel G. Knierim

Stochastic Flash Analog-to-Digital Conversion

A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual comparator trip points. A stochastic flash ADC uses random comparator offset to set the trip points. Since the comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using comparators that are implemented as digital cells produces a large variation of comparator offset. Typically, this is considered a disadvantage, but in our case, this large standard deviation of offset is used to set the input signal range. By designing an ADC that is made up entirely of digital cells, it is a natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer function described by a Gaussian cumulative distribution function, and a technique is presented that reduces this nonlinearity by changing the overall transfer function of the stochastic flash ADC. A test chip is fabricated in 0.18- CMOS to demonstrate the concept.

A 6b stochastic flash analog-to-digital converter without calibration or reference ladder

A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.

Design Considerations for Stochastic Analog-to-Digital Conversion

Using knowledge of the random nature of device mismatch it is possible to employ stochastic techniques in an ADC. This would allow the use of many smaller and less accurate components, and may make it possible to save power and area while maintaining accuracy. Additional benefits include high scalability and high yield with process variation. Various design considerations are suggested that must be addressed to design a successful stochastic ADC and an example calibration and decoding scheme is described.