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Dive into the research topics where Daniel K. Sparacin is active.

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Featured researches published by Daniel K. Sparacin.


Journal of Lightwave Technology | 2005

Silicon waveguide sidewall smoothing by wet chemical oxidation

Daniel K. Sparacin; Steven J. Spector; Lionel C. Kimerling

This paper reports a new and more efficient Si waveguide sidewall smoothing process using wet chemical oxidation. Sidewall roughness is a major source of loss and an impediment to realizing high-transmission Si waveguides. The postetch multistepped approach allows for efficient smoothing (in terms of roughness amplitude reduction to material consumption) by continuous oxidation in the fast reaction-limited regime. This method reduces waveguide transmission loss without sacrificing dimensional integrity or thermal budget. In this proof-of-concept work, Si waveguide sidewall loss has been reduced from 9.2 to 1.9 dB/cm.


Journal of Applied Physics | 2006

Surface-energy-driven dewetting theory of silicon-on-insulator agglomeration

David T. Danielson; Daniel K. Sparacin; Lionel C. Kimerling

The thermal agglomeration of ultrathin (<30nm) single crystal silicon-on-insulator (SOI) films is a morphological evolution phenomenon with practical and scientific importance. This materials phenomenon represents both a critical process limitation for the fabrication of advanced ultrathin SOI-based semiconductor devices as well as a scientifically interesting morphological evolution problem. Investigations to date have attributed this phenomenon to a stress-induced morphological instability. In this paper, we demonstrate that SOI agglomeration is a surface-energy-driven dewetting phenomenon. Specifically, we propose that agglomeration occurs via a two-step surface-energy-driven mechanism consisting of (1) defect-mediated film void nucleation and (2) surface-diffusion-limited film dewetting via capillary edge and generalized Rayleigh instabilities. We show that this theory can explain all of the key experimental observations from the SOI agglomeration literature, including the locations of agglomeration i...


optical fiber communication conference | 2007

Demonstration of a Fourth-Order Pole-Zero Optical Filter Integrated Using CMOS Processes

Mahmoud Rasras; Douglas M. Gill; Sanjay Patel; Kun-Yii Tu; Young-Kai Chen; Alice E. White; Andrew Pomerene; Daniel N. Carothers; Michael J. Grove; Daniel K. Sparacin; Mark Beals; Lionel C. Kimerling

We demonstrate a compact fully tunable narrowband fourth-order pole-zero optical filter that is fabricated in a silicon complementary-metal-oxide-semiconductor foundry. The filter is implemented using silicon on oxide channel waveguides and consists of a Mach-Zehnder interferometer with two ring resonator all-pass filters (APFs) on each arm. The filter architecture is based on the sum and difference of the APFs responses. The ring resonators introduce a nonlinear phase response in each arm that allows carving narrow frequency bands out of a broad spectrum. In this paper, we demonstrate a 3-dB filter bandwidth of 1.0 GHz with a stopband rejection of better than 25 dB. The filter free spectral range is 16.5 GHz. Thermooptic phase shifters are used to tune the filter. As silicon has a large thermooptic coefficient compared to silica, the demonstrated filter requires a low tuning power of less than 300 mW. In addition, this filter is compact with dimensions 25 times smaller than the same filter would be if it were made using standard silica on silicon waveguides with a 0.8% step index contrast


Proceedings of SPIE, the International Society for Optical Engineering | 2008

Process flow innovations for photonic device integration in CMOS

Mark Beals; J. Michel; Jifeng Liu; Donghwan Ahn; Daniel K. Sparacin; Rong Sun; Ching-yin Hong; Lionel C. Kimerling; Andrew Pomerene; Daniel N. Carothers; James Beattie; Anthony Kopa; Alyssa B. Apsel; Mahmoud Rasras; Douglas M. Gill; Sanjay Patel; K.Y. Tu; Y.K. Chen; A. E. White

Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate complimentary materials and process sequences required for high index contrast photonic components all within a single CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems, Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit (AS_EPIC). Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer application. This presentation will review the latest advances of the passive and active photonic devices developed and the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.


Applied Physics Letters | 2009

Transparent amorphous silicon channel waveguides with silicon nitride intercladding layer

Rong Sun; Kevin A. McComber; Jing Cheng; Daniel K. Sparacin; Mark Beals; Lionel C. Kimerling

We have experimentally demonstrated single mode amorphous silicon channel waveguides with low optical transmission loss of 2.7±0.4 dB/cm for TE mode in the 1550 nm range. This result was achieved by using hydrogen passivation of a-Si dangling bonds and a thin, low loss silicon nitride intercladding layer prepared by plasma enhanced chemical vapor deposition between the waveguide core and the oxide cladding layer. The silicon nitride intercladding layer reduces waveguide sidewall roughness scattering and preserves the hydrogen passivation.


international conference on group iv photonics | 2006

Low-Loss Amorphous Silicon Channel Waveguides for Integrated Photonics

Daniel K. Sparacin; Rong Sun; Anuradha M. Agarwal; Mark Beals; J. Michel; Lionel C. Kimerling; T.J. Conway; Andrew Pomerene; Daniel N. Carothers; Michael J. Grove; D.M. Gill; Mahmoud S. Rasras; Sanjay Patel; Alice E. White

Amorphous silicon (a-Si), single-mode, channel waveguides were fabricated and measured with transmission losses as low as 6.5 dB/cm for the TE mode and 4.5 dB/cm for the TM mode. Variations in the PECVD a-Si deposition conditions yielded a-Si materials with bulk losses <1 dB/cm


Optics Letters | 2005

Trimming of microring resonators by photo-oxidation of a plasma-polymerized organosilane cladding material

Daniel K. Sparacin; Ching-yin Hong; Lionel C. Kimerling; John P. Lock; Karen K. Gleason

As the complexity of microphotonic devices grows, the ability to precisely trim microring resonators becomes increasingly important. Photo-oxidation trimming uses UV irradiation to oxidize a cladding layer composed of polymerized hexamethyldisilane (6M2S) deposited with plasma-enhanced chemical vapor deposition (PECVD). PECVD 6M2S has optical properties that are compatible with microring devices, and its high cross linking renders it insoluble. Photo-oxidation decreases the refractive index of PECVD 6M2S by nearly 4%, permitting large resonance shifts that are not feasible with thermal trimming techniques. Resonance shifts from single-mode, 100 microm diameter Si3N4 (n =2.2) rings were as large as 12.8 nm for the TE mode and 23.5 nm for the TM mode.


optical fiber communication conference | 2006

Tunable Narrowband Optical Filter in CMOS

Mahmoud Rasras; D.M. Gill; Sanjay Patel; Alice E. White; Kun-Yii Tu; Young-Kai Chen; Daniel N. Carothers; Andrew Pomerene; Michael J. Grove; Daniel K. Sparacin; Mark Beals; Lionel C. Kimerling

We demonstrate a compact, fully tunable, narrowband (1GHz) 4thorder pole/zero optical filter that is fabricated in a silicon complementary metal oxide semiconductor foundry.


Journal of Lightwave Technology | 2015

30-Gb/s Optical Link Combining Heterogeneously Integrated III–V/Si Photonics With 32-nm CMOS Circuits

Nicolas Dupuis; Benjamin G. Lee; Jonathan E. Proesel; Alexander V. Rylyakov; Renato Rimolo-Donadio; Christian W. Baks; Abhijeet Ardey; Clint L. Schow; Anand Ramaswamy; Jonathan E. Roth; Robert S. Guzzon; Brian R. Koch; Daniel K. Sparacin; Greg A. Fish

We present a silicon photonics optical link utilizing heterogeneously integrated photonic devices driven by low-power advanced 32-nm CMOS integrated circuits. The photonic components include a quantum-confined Stark effect electroabsorption modulator and an edge-coupled waveguide photodetector, both made of III-V material wafer bonded on silicon-on-insulator wafers. The photonic devices are wire bonded to the CMOS chips and mounted on a custom PCB card for testing. We demonstrate an error-free operation at data rates up to 30 Gb/s and transmission over 10 km at 25 Gb/s with no measured sensitivity penalty and a timing margin penalty of 0.2 UI.


Proceedings of SPIE, the International Society for Optical Engineering | 2007

Advances in fully CMOS integrated photonic devices

J. Liu; Donghwan Ahn; Daniel K. Sparacin; Rong Sun; Ching-yin Hong; Wojciech P. Giziewicz; Mark Beals; Lionel C. Kimerling; A. Kopa; Alyssa B. Apsel; Mahmoud Rasras; Douglas M. Gill; Sanjay Patel; K. Y. Tu; Y. K. Chen; A. E. White; Andrew Pomerene; Daniel N. Carothers; M. J. Grove

The complete integration of photonic devices into a CMOS process flow will enable low cost photonic functionality within electronic circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, Cornell University, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application specific, electronic-photonic integrated circuit (AS-EPIC). The first phase of the program was dedicated to photonics device designs, CMOS process flow integration, and basic electronic functionality. We will present the latest results on the performance of waveguide integrated detectors, and tunable optical filters.

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Lionel C. Kimerling

California Institute of Technology

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Mark Beals

Massachusetts Institute of Technology

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