Daniele Perucchini

An impact-based approach for the analysis of cascading effects in critical infrastructures

An original methodology for the analysis of cascading effects in critical infrastructure is hereby presented. First of all, a rationale to identify elements (items) of daily life of citizens whose lack would cause a considerable impact on the quality of life of population is discussed. Then, a methodology to foresee domino effects among infrastructures is described. This methodology allows to account for domino effects in the identification of critical infrastructures, based on the impact on citizens of the outage of the various infrastructures, and supports an effective implementation of EU Directive 114/08/CE on the identification and protection of critical infrastructures.

Characterization of timing signals and clocks

The characteristics of timing signals at the output of autonomous and slave clocks are thoroughly investigated : first, a mathematical model of timing signals is introduced, then models for describing autonomous and slave clocks are presented whereby an analysis of their behaviour in a synchronization network is carried out. Further, two commonly used measurement configurations are described in order to identify the measurement set-ups more useful for telecommunication applications ; the most frequently used quantities for characterizing time and frequency stability are introduced and deeply investigated. Finally, the stability quantities behaviour both for autonomous and slave clocks is studied, with the aim at providing synchronization network designers with powerful tools for network planning and for assessing network performance.

Evaluation of near-end crosstalk noise affecting ADSL systems

One of the major concerns related to the introduction of asymmetric digital subscriber line (ADSL) systems is the compatibility between such systems and transmission systems already deployed in the access network. In particular, three main noise sources must be considered, namely, near-end crosstalk (NEXT), far-end crosstalk (FEXT) and impulsive noise. The problem of evaluating the amount of NEXT noise on ADSL receivers due to DSL, HDSL, E1 and POTS disturbers is considered. Firstly, mathematical expressions for the power spectral density (PSD) of the above disturbers are provided and an expression for evaluating NEXT noise PSD is presented. Finally, the results obtained considering different scenarios (i.e., low-noise, high-noise and worst case NEXT coupling), are reported and discussed with the aim of providing useful information and guidelines for the introduction of ASDL systems in the access network.<<ETX>>

Different behaviour of frequency stability measures in independent and synchronized clocks: theoretical analysis and measurement results

The problem of characterizing the synchronization performance plays a central role in the design of SDH based telecommunication networks. Moreover, establishing the suitable quantities for characterizing the frequency stability of timing signals, together with their measurement configurations, is still an open issue in the standardization committees. We deal with some of the most important frequency stability quantities. An analysis envisaging the possibility to theoretically assess such quantities is carried out showing that substantial differences are expected in the behaviour of the above mentioned quantities, depending on the measurement configuration adopted. Besides, a high precision measurement set-up was used to derive experimental results which confirm the main theoretical conclusions and, at the same time, provide a good insight into the behaviour of various stability measures.<<ETX>>

Root mean square time interval error accumulation along slave clock chains

The main aspects of synchronization strategies suitable for application to synchronous digital hierarchy (SDH) based transport networks are discussed, with particular emphasis on the relative phase stability of distributed timing signals. Based on a mathematical model of slave clocks and a reference structure of the synchronization network, a theoretical approach to the calculation of root mean square relative time interval error between SDH equipment clocks and the primary reference clock of the network is described. The comparison of results from extensive calculations allows more insight on the behavior of cascaded slave clocks and the derivation of important suggestions for the synchronization network design.<<ETX>>

Clock stability measures for the assessment of synchronization network performance

At present, one of the major open issues related to the implementation of SDH based transport networks is the design of a suitable synchronization network, required in order to exploit fully the capabilities offered by the new hierarchy. In fact, unacceptable signal degradation may result if too loose requirements are set in the specification of clocks and synchronization network architecture: hence the problem of characterizing synchronization network performance plays a central role in synchronization network design. In this paper, starting from a general model of timing signals generated by actual clocks, frequency and time domain quantities suitable for characterizing frequency and time stability are presented. Then the problem of assessing synchronization network performance is investigated, analysing with particular care the measurement configurations usable for the evaluation of the time domain quantities. Finally, results from computer based calculations performed to evaluate Allan variance behaviour in different measurement configurations are presented.

Synchronization of SDH networks: slave clocks model and stability measures

In SDH-(synchronous digital hierarchy-)based transport networks, the synchronization problem must be carefully considered, in order to guarantee good performance in transporting PDH (plesiasynchronous digital hierarchy) tributaries. In particular, careful design of equipment synchronization strategies is required in order to limit pointer adjustments in SDH streams. A variety of quantities able to characterize clock performance, is presented, and it is shown that the root mean square, relative time interval error is a reliable quantity for characterizing slave clock behavior in ideal operation. An expression for such a quantity is suggested.<<ETX>>

Jitter and wander performance in synchronization distribution chains

Clock phase noise models based on theoretical analysis and experimental evidence are presented and used to calculate the amount of jitter and wander that, due to both oscillator internal noise and medium temperature variations, accumulate at the end of typical synchronization distribution chains. Chain timing performance are evaluated in terms of two well known stability quantities, i.e., time deviation and maximum time interval error, by using an approach based on the generation of time error data starting from the frequency domain characterization of clock phase noise.

Clock stability measure dependence on time error sampling period

The introduction of SDH based networks rises new important synchronization issues to be carefully investigated. In particular, the telecommunication standard bodies are mainly considering, for the specification of clocks, five frequency stability quantities: Allan (1991) variance, modified Allan variance, time variance, root mean square of the time interval error and maximum time interval error. The influence of time error measurement sampling period on the behaviour of these quantities is analyzed. Computer simulation and experimental measurement results are reported. With the aim of providing useful information for specification design. The results obtained show that the modified Allan variance and time variance behaviour is substantially dependent on the chosen measurement sampling period in the observation interval regions where white phase noise dominates.

Impact of slave clock internal noise on Allan variance and root mean square time interval error measurements

Starting from a slave clock model, results describing the impact of clock internal noises on TIErms and ADEV are provided, based on theoretical analysis, computer simulations and experimental measurements. Comparison of the obtained results allows to validate the numerical approach used for calculations.<<ETX>>