Dapeng Jin

FPGA - Based Compute Nodes for the PANDA Experiment at FAIR

PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10**7 /s and data rates of several 100 Gb Is. FPGA based compute nodes with multi-Gbit/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Each board is equipped with 5 Virtex4 FX60 FPGAs. High bandwidth connectivity is provided by four Gbit Ethernet links and 8 additional optical links connected to RocketIO ports. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane.

ATCA-based computation platform for data acquisition and triggering in particle physics experiments

An ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each compute node (CN) which appears as a field replaceable unit (FRU) in an ATCA shelf, features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytes DDR2 memory. Connectivity is provided with 8 optical links and 5 Gigabit Ethernet ports, which are mounted on each board to receive data from detectors and forward results to outer shelves or PC farms with attached mass storage. Fast point-to-point on-board interconnections between FPGAs as well as the full-mesh shelf backplane provide flexibility and high bandwidth to partition algorithms and correlate results among them. The system represents a highly reconfigurable and scalable solution for multiple applications.

Hardware/software co-design of an ATCA-based computation platform for data acquisition and triggering

An ATCA-based computation platform for data acquisition and trigger(TDAQ) applications has been developed for multiple future projects such as PANDA, HADES, and BESIII. Each Compute Node (CN) appears as one of the fourteen Field Replaceable Units (FRU) in an ATCA shelf, which in total features a high performance of 1890 Gbps inter-FPGA onboard channels, 1456 Gbps inter-board backplane connections, 728 Gbps full-duplex optical links, 70 Gbps Ethernet, 140 GBytes DDR2 SDRAM, and all computing resources of 70 Xilinx Virtex-4 FX60 FPGAs. Corresponding to the system architecture, a hardware/software co-design approach is proposed to ease and accelerate the development for different experiments. In the uniform system design, application-specific computation is to be implemented as customized hardware co-processors, while the embedded PowerPC processor takes charge of flexible slow controls and transmission protocol processing.

Application of ATCA in trigger and DAQ system for experimental physics

An ATCA-based trigger and data acquisition and trigger applications for particle physics experiments has been developed. Each Compute Node features 5 Xilinx Virtex-4 FX60 FPGA chips and up to 10 GBytes DDR2 memory. High bandwidth connectivity is provided by 8 additional optical links using RocketIO ports and 5 Gbit Ethernet links to receive data from front-end electronics and transmit the data passed trigger to mass storage. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane. A prototype has been set up and some characters have been tested.

Trigger System of BESIII

The trigger system of Beijing Spectrometer III, part of the upgrade of Beijing Electron Positron Collider, has been designed and implemented, and is ready for installation. This paper describes briefly the system components, its characteristics, and some technical issues. The system consists mainly of four parts: MDC (drift chamber) tracking subsystem, EMC (electromagnetic calorimeter) subsystem, TOF (time of flight) subsystem and global trigger. Some highlights in designing of this system includes: trigger scheme optimization with software simulation; optical transmission between trigger and FEEs to realize isolation with FEEs to avoid ground loop current interference; designed with most latest FPGA (Xilinx Spartan 3, VirtexII Pro...) for simplicity, high reliability and easy maintenance and hence smaller system; FPGA in-system programming or firmware online downloadable via onboard, panel connector and/or VME bus for modification flexibility during commissioning. Different from the usual fix delay data transmission from FEE to trigger, the RocketIO has been used as SEDES.

A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments

A high-performance computation platform based on field-programmable gate arrays targets nuclear and particle physics experiment applications. The system can be constructed or scaled into a supercomputer-equivalent size for detector data processing by inserting compute nodes into advanced telecommunications computing architecture (ATCA) crates. Among the case study results are that one ATCA crate can provide a computation capability equivalent to hundreds of commodity PCs for Hades online particle track reconstruction and Cherenkov ring recognition.

Developments for the PANDA online high level trigger

The PANDA detector is a state-of-the-art general-purpose detector for physics with high luminosity cooled antiproton beams, planed to operate at the FAIR facility in Darmstadt, Germany. The central detector includes a silicon Micro Vertex Detector (MVD) and a Straw Tube Tracker (STT) or Time Projection Chamber (TPC). The electromagnetic lead tungstate calorimeter(EMC) provides almost 4π spatial coverage, good granularity and high energy resolution for electromagnetic showers measurement. A DIRC Cherenkov detector serves for particle identification. A novel trigger-less data push data architecture for the PANDA trigger and data acquisition system is proposed requiring the data from readout module to be processed in real-time to reconstruct charged tracks, electromagnetic showers and calculating PID parameters. This presentation shows results from the development of online high level trigger algorithms. A track finding algorithm for helix track reconstruction in the solenoidal field and a cluster finder for searching clusters in the EMC have been developed with special considerations for the implementation on the FPGA based Compute Node platform which has been developed for PANDA[1]. Performance parameters such as momentum and spatial resolution for the helix track finder, energy and spatial resolution for the EMC cluster finder will be presented. With respect to the FPGA implementation, the partition strategy based on the readout electronics layout and the Compute Node processing architecture will be presented.

An ATCA and FPGA-based Data Processing Unit for PANDA Experiment

An ATCA and FPGA-based Data Processing Unit for PANDA Experiment has been developed. The Unit features 5 Xilinx Virtex-4 FX60 FPGA chips and up to 10 GBytes DDR2 memory. High bandwidth connectivity is provided by 8 additional optical links using RocketIO ports and 5 Gbit Ethernet links to receive data from front-end electronics and transmit the data passed high level trigger to mass storage. A single ATCA shelf can host up to 14 boards which are interconnected via a full mesh backplane. A prototype system has been set up and some tests have been made.

Trigger algorithm development on FPGA-based Compute Nodes

Based on the ATCA computation architecture and Compute Nodes (CN), investigation and implementation work has been being executed for HADES and PANDA trigger algorithms. We present our designs for HADES track reconstruction processing, Cherenkov ring recognition, Time-Of-Flight processing, electromagnetic shower recognition, and the PANDA straw tube tracking algorithm. They will appear as co-processors in the uniform system design to undertake the detector-specific computing. The algorithm principles will be explained and hardware designs are described in the paper. The current progress reveals the feasibility to implement these algorithms on FPGAs. Also experimental results demonstrate the performance speedup when compared to alternative software solutions, as well as the potential capability of high-speed parallel/pipelined processing in Data Acquisition and Trigger systems.

PANDA EMC Trigger and Data Acquisition Algorithms Development

xuhao@ihep.ac.cnThe PANDA detector is a general purposed hadron spectrum planed to operate at the FAIR facilityin Darmstadt, Germany. The PANDA electromagnetic calorimeter(EMC) employs 11360 PWO-II crystals for barrel module, 3600 for forward module and 592 for backward module providing4p spatial coverage, good granularity and high energy resolution. A novel self-trigger data pushdata architecture for the PANDA data acquisition system requiring the data from EMC readoutelectronics to be processed on the fly to reconstruct electromagnetic shower. Features extractedfrom the electromagnetic shower combine with information from other detectors such as trackingand Cherenkov detectors in order to discriminate between photons, electron and hadrons. ThePANDA EMC detector performance, proposed readout electronics and offline reconstruction al-gorithms are studied and an adaptive EMC DAQ schematic is proposed based on an FPGA basedCompute Node which provides high bandwidth flexible connections between processing modules,up to 10GByte DDR2 per board for data buffering and five large capacity V4FX60 FPGAs forsophisticated algorithms applications. The algorithms partition strategy is proposed consideringthe readout electronics layout and the Compute Node based processing architecture. The functionverification and performance evaluation methods for the algorithms are also studied.