Daqing Zou

Phase-shifting analysis in moire interferometry and its applications in electronic packaging

In layered materials and structures, it is essential to observe stress and strain concentrations, strain gradients, failure initiation and growth, and local microstructure evolution. In this study, an innovative phase-shifting technique is proposed, coupled with image-processing software, to investigate several interesting problems in electronic packaging. A window-based graphics interface for phase shifting in a moire interferometry system is introduced. The phase shifting is accomplished by driving the reference grating in the moire interferometry system with a low-voltage piezo stack. Three images obtained from three shifts and the original image are used to derive the phase diagram, which is used for displacement and strain calculations. Automatic fringe numbering is achieved by the phase shifting, which significantly simplifies the traditional fringe-counting and -ranking process. The strain calculation is also automatic, utilizing the space derivative of the displacement. A three- point bending beam is used for the demonstration. In addition, a power plastic IC package and a flip-chip package are selected to demonstrate the power of the system. A nanoscale deformation field is obtained for both the corner area and the flip-chip solder balls.

Investigation of interfacial fracture behavior of a flip-chip package under a constant concentrated load

In this paper, the interfacial fracture behavior of a flip-chip package subjected to a constant concentrated line load was investigated using a unique six-axis submicron tester coupled with a high density laser moire interferometry. The real-scale three-point bending flip-chip specimen, capable of measuring the crack growth rate (along the interface) and the interfacial fracture toughness was developed. The results show that the crack propagation along the interface of the passivated silicon chip/underfill under a constant concentrated load can be categorized into three stages occurring in the order mentioned with obvious transition points between them: (1) stable crack propagation stage; (2) unstable crack propagation stage; (3) quasicrack arrest stage. The moire interferometry technique was used to monitor and measure the crack length during the test. The crack growth rate along the interface of the passivated silicon chip/underfill was calculated in terms of the load line deflection versus time curve obtained from the test. In addition, the relationship between the crack length and the load line deflection was calibrated by using finite element analysis. The near tip displacement fields of the flip-chip package was also determined by the same method. The energy release rate was computed by using these near tip displacement variables through an analytical expression derived by authors. The interfacial fracture toughness G/sub c/ was determined by calculating the energy release rate corresponding to the crack length at the quasicrack arrest stage measured in the test. The underfill/chip passivation fracture toughness G/sub c/ and the phase angle /spl phi/ for the flip-chip package used in our experiments are about 35 J/m/sup 2/ and -65/spl deg/, respectively.

A study of the mixed-mode interfacial fracture toughness of adhesive joints using a multiaxial fatigue tester

In this paper, a new technique is introduced for the control of the far field and mixed-mode crack tip of a single lap shear specimen with a crack along the interface. An investigation has been conducted to use one single lap shear specimen to obtain a series of values of interfacial fracture toughness as a function of the mixed-mode phase angle. The interfacial fracture behavior of the single lap shear specimen subjected to multiaxial concentrated line loads was investigated using a unique six-axis submicron tester coupled with a high density laser moire interferometer. The six-axis submicron tester was used to provide the displacement-controlled multiaxial concentrated line loads, whereas the moire interferometry technique was used to monitor the crack length during the test. In addition, a finite element technique was simultaneously used to determine the near crack tip displacement fields of the single lap shear specimen. The interfacial fracture toughness and phase angle were computed by using these near tip displacement variables through the analytical energy release rate and phase angle expressions derived by the authors. The results show that the facilities and methodology used in the current study can indeed be proved to possess the ability to control the far field and the mixed-mode conditions at crack tip, and to efficiently perform the mixed-mode fracture test.

Processing mechanics for flip-chip assemblies

Abstract In this paper, a non-linear finite element framework has been implemented to simulate the sequential build-up of a flip-chip package. A generalized deformation model with element removal and addition is used to activate and deactivate the underfill material layer to simulate flip-chip package fabrication. Using process models, one can determine the warpage stresses at any intermediate stage in the process. In addition, topological change is also considered in order to model the sequential steps during the flip-chip assembly. Geometric and material nonlinearity which includes the creep behavior of underfill and solder balls, and temperature-dependent material properties are considered. Different stress-free temperatures for different elements in the same model are used to simulate practical manufacturing process-induced thermal residual stress field in the chip assembly. This approach (the processing model established in this paper) is in contrast to the non-processing model employed by many researchers, which is shown to yield overly conservative and sometimes erroneous results, leading to non-optimal design solutions. From the finite element analysis, it is found that the strains and deflections obtained from the non-processing model are generally smaller than those obtained from the processing model due to the negligence of the bonding process-induced residual strains and warpage. Furthermore, the fatigue life for the outmost solder ball predicted by the processing model is much shorter than that predicted by the non processing model based on the Coffin–Manson equation. On the other hand, in order to prove the soundness of the framework established in this paper, the test results obtained by using the laser moireinterferometry technique are compared with the results achieved from the proposed numerical analysis vehicle. It is shown that the deformation values of the flip-chip package predicted from the finite element analysis are in a good agreement with those obtained from the test.

Evaluation of interfacial fracture toughness of a flip-chip package and a bimaterial system by a combined experimental and numerical method

Abstract In this paper, the interfacial fracture toughness of a flip-chip package subjected to a constant concentrated line load and a bimaterial system under thermal loading condition were evaluated using a unique six-axis submicron tester, a thermal vacuum chamber and FEM modeling coupled with a high density laser moire interferometry. The six-axis submicron tester was used to provide a constant concentrated line load, whereas the moire interferometry technique was used to monitor the crack length during the test. In addition, a finite element technique was simultaneously used to determine the near crack tip displacement fields of the specimens. The interfacial fracture toughness and phase angle were computed by using these near tip displacement variables through the analytical energy release rate and phase angle expressions derived by authors. The interfacial fracture toughness and the phase angle of the flip-chip package considered at the interface where the passivated silicon chip meets the underfill are 35 J/m 2 and −65°, respectively, while the interfacial fracture toughness and the phase angle of the tested bimaterial specimen at the interface of the molding compound/silicon with the crack length of 3.3 mm under the temperature rise thermal load from room temperature (20°C) to 138°C are 20.02 J/m 2 and −54.8°, respectively.

Study of delaminated plastic packages by high temperature Moire and finite element method

In the current study, 1200 l/mm gratings are replicated at elevated temperatures onto the cross sections of two delaminated plastic packages: a thin quad flatpack plastic package (TQFPP) and a power small outline plastic package (PSOPP). The specimens are measured at room temperature for thermal deformation induced by cooling process. The finite element models are used to simulate the cooling process and the results are compared with the Moire interferometry results. The finite element models with different delaminations between die and die attach are used to simulate the fringe patterns obtained from Moire interferometry. It was found that the delamination size can be estimated by the combination of Moire technique and finite element method. The finite element model, once verified, can then be used in making cost effective decisions in plastic packaging design and processing.

Resolving displacement field of solder ball in flip-chip package by both phase shifting moire interferometry and FEM modeling

In this paper, phase shifting moire interferometry was used to resolve the deformation field of solder balls in a flip-chip package under thermal loading condition. A nanoscale deformation field of the outmost solder ball was obtained by using the proposed phase shifting technique associated with the corresponding image processing software. In addition, a nonlinear finite element technique, in which the viscoelastic material properties of underfill and the viscoplastic material properties of solder balls were considered was also adapted to simulate the global displacement field - the whole cross-section of the flip-chip package and the local displacement field - the whole cross-section of one solder ball in the flip-chip package. By comparing the predicted deformation values of the flip-chip package obtained from the finite element analysis with the test data obtained from the laser moire interferometry technique, good agreement is obtained. In particular, the nanoscale displacement contours of the solder ball both in x and y directions obtained from the phase shifting technique show much more similar distribution patterns compared with those modeled by the finite element method.

CTE-measurement and delamination growth by a real time Moire technique

In this study, a real time moire interferometry technique was presented. CTE (coefficient of thermal expansion) and glass transfer temperature (Tg) measurements of a molding compound were conducted with the aid of a recently developed vacuum thermal chamber and a computer imaging analysis system. This technique was also applied to the study of the thermo-mechanical deformation of a silicon/molding compound bimaterial with an interface delamination. The fringe patterns of the thermo-mechanical deformation were presented. The phase angle of the interface delamination were calculated and discussed.

Investigation of nonlinear behaviors of packaging materials and its application to a flip-chip package

The creep behavior of a flip-chip package under thermal load is studied using finite element models and high density laser moire interferometry. FEA accuracy strongly depends on a reliable input material database, and thus a series of tests were first carried out using a 6-axis mini fatigue tester for eutectic 63Sn37Pb solder alloy and FP4526 underfill. From the test data, six FEA models are used to simulate creep under elastic, elastic-plastic, viscoelastic or viscoplastic behavior for both solder balls and underfill. The results show that solder and underfill nonlinear material behavior do not have a major effect on flip-chip warpage, but do affect the stress. In all visco FEA models, Von Mises stresses at the corner or center of the outermost solder ball greatly decrease. However, Von Mises stresses predicted by elastic-plastic and elastic models remain unchanged during the temperature holding time and are much higher than those from visco FEA models. Although solder ball stresses predicted by visco models have no major difference, this is not true for underfill. By comparing FEA results, it is suggested that the strain rate-dependent model is used to describe underfill creep behavior. However, the inelastic equivalent strain which is usually used as the fatigue life prediction parameter also shows big differences between FEA models, and thus a suitable model must be carefully chosen for accurate fatigue life prediction. Furthermore, flip-chip package creep is measured by real-time moire interferometry. The FEA model package deformation values are compared with the laser moire interferometry data and are in good agreement.

High temperature deformation of area array packages by moire interferometry/FEM hybrid method

In this study, moire interferometry and experimental/FEM hybrid method were applied in the thermal deformation analysis of several area array packages. High frequency gratings of 1200 l/mm and 600 l/mm were replicated onto the cross sections of packages at the elevated temperature of 80/spl deg/C or 160/spl deg/C. These packages include an OMPAC BGA and a flip-chip BGA. The thermal deformation of these packages were measured by moire interferometry. Warpage of the packaging systems was measured and the effects of the bonding, encapsulation, soldering, and geometry on the deformation were discussed. The strain distributions inside the solder joints were analyzed by both moire interferometry and experimental/FEM hybrid method.