Dariusz Koscielnik

Designing Time-to-Digital Converter for Asynchronous ADCs

Time-to-digital converter designing and analysis for asynchronous ADCs is discussed in the paper. The proposed ADC utilizes two-level conversion scheme consisting in duty-cycle modulation and subsequent time-to-digital conversion (TDC). Three concepts of the asynchronous ADC digital serial output interface are presented. The comparison of minimum transmission rates of the serial output port(s) for each concept is carried out. Finally, the procedure of the evaluation of key ADC design parameters for the speech signal supporting a possible original input signal recovery is exemplified.

Uncertainty of asynchronous analog-to-digital converter output state

The fundamental difference between the classical signal value quantization and the quantization of the asynchronous time intervals is that there is only one quantization noise component in the former instead of two independent components in the latter. The quantization of a given time interval may result in two different values of a digital code depending on the phase of the reference clock in relation to the beginning of the discretized time interval. The problem of uncertainty of state on the output of asynchronous analog-to-digital converter (A-ADC) is illustrated and analyzed in the paper. It is shown that the noise introduced by the clock-based quantization in A-ADCs is 3 dB higher than that in the conventional ADCs. As a result, the resolution of the A-ADC is a half bit worse than the resolution of the classical ADC with the signal value quantization. The time quantization of the asynchronous time interval may be modeled by random rounding operation. The advantages and disadvantages of clock-based asynchronous time quantization is discussed in details.

A clockless time-to-digital converter

Existing implementations of time-to-digital converters are based on the use of reference clocks. In the paper, a new method of clockless time-to-digital conversion (TDC) is proposed where the discretized time interval is first converted to the corresponding charge packet, and next processed in the charge domain by successive charge redistribution. The proposed circuit configuration is extremely simple and contains only binary-weighted capacitor array, current source, group of controlled switches, 2 comparators and asynchronous state machine. The TDC is self-timed and does not contain the DAC.

A new method of charge-to-digital conversion

A new method of charge-to-digital conversion based on the binary-weighted charge redistribution is presented in the paper. The proposed method takes advantage of a binary search algorithm similar to the other successive approximation schemes. The novelty of presented approach consists in a lack of a digital-to-analog converter, and more importantly, also in eliminating a clock that controls converter operation. The circuit diagram for the self-timed charge-to-digital conversion that implements the proposed method of charge redistribution is discussed in detail.

Natural compression and expansion characteristics of asynchronous Sigma-Delta ADC

The paper analyzes the impact of non-linearity of asynchronous Sigma-Delta analog-to-digital converter (ASD-ADC) characteristics on the quantization process. The ASD-ADC is considered as time-interleaved multi-resolution converter that employs two different characteristics for signal processing alternately. As shown in the paper, the classical uniform quantization of the asynchronous Sigma-Delta modulator (ASDM) output signal by time-to-digital converter is ineffective due to the different shapes of ASDM characteristics that provide disparity of converter resolution transformed into the signal value domain. A need to introduce extra compensation techniques to cope with the problem of balancing the ASD-ADC resolution and shaping the signal-to-noise ratio is emphasized.

A programmable controller for combustion engines used in race cars

An engine of a race car is exposed to permanent modifications. As a consequence of realised modifications, the enginepsilas parameters are still changing. A correct control of the supply of such an engine needs many corrections of the single parameters and sometimes also of the algorithms that are used. In this document, we have presented the structure and the functioning of the programmable controller for combustion engines with spark ignition, designed for a company executing the tuning of sports cars. In the first part, the method of connection of the computer with the target system has been presented. The second part has been dedicated to the working algorithm of the controller and the structures of data. The summary presents the possible directions of further development of this project.

Simulation Study of IEEE 802.11e Wireless LAN - Enhancements for Real Time Applications

The new IEEE 802.11 standard version, denoted by 802.11e, was developed in order to introduce mechanisms enabling handling of real time applications. In order to achieve the goal, the transmission channel access control procedure was modified. The new approach consists in distinguishing the time after which packet transmission of a certain class may begin. The developed mechanism is not yet deterministic, but based on the principle of increasing the probability of success. In consequence, quality of service levels (QoS) guaranteed by the network to different applications may be strongly dependent not only on the type and intensity of input traffic, but also on up-to-date results of random processes realised in different stations. The first part of this paper contains short descriptions of the original and modified method of controlling access to the transmission channel. Using the further presented results of simulation tests it is possible to determine system operation intervals in which the network guarantees the required quality of service to traffic streams of a given class. The summary contains most important conclusions from the comparison of working principles of both mechanisms as well as the executed experiments

Modeling event-driven successive charge redistribution in ADC with varying rate of charge transfer

The paper addresses a technique of the asynchronous (clockless) analog-to-digital conversion based on the event-driven successive charge redistribution (SCR) in the binary-scaled capacitor array. A significant point is that the event-driven SCR-ADC differs from the known techniques of charge redistribution used in classical ADCs with the binary-weighted capacitors because the charge transfer is self-timed in the former whereas it is clock-driven in the latter. Former publications on event-driven SCR-ADC were based on constant-rate charge redistribution between the source and the destination capacitors realized by the current source in the number of steps defined by converter resolution. The contribution of the present study is the analysis of the event-based SCR scheme forced by voltage difference between both capacitors which decreases as the charge redistribution proceeds. The aim of the analysis is the evaluation of the conversion time of the relevant converter.

Influence of the hidden stations and the exposed station for the throughput of the LR-WPAN

This article presents wireless personal area networks with low transmission rate, utilized more and more often in industrial or alarm systems, as well as in sensor networks. The structure of these systems and available ways of transmission are defined by the IEEE 802.15.4 standard. The second part of the paper contains the description of simulation tests that have been realized. Their results make available an evaluation of the effective throughput of the LR-WPAN and the resistance to the phenomenon of hidden station and the exposed station.

Simulation study of the influence of hidden stations for the quality of service in the IEEE802.11e WLAN

The new IEEE 802.11 standard version, denoted by 802.11e, was developed in order to introduce mechanisms enabling handling of real time applications in the network. The proper work of the EDCF protocol is influenced by the presence of hidden stations in the network. These nodes may produce a significant increase of the number of collisions. The first part of this paper contains short descriptions of the traditional and modified methods of control of access to the transmission channel. The presented results of simulation tests make possible to determine the influence of the presence of a hidden station for the performances of the entire system and the efficiency of the EDCF mechanism. In the summary we have presented the most important conclusions from the experiments that has been performed.