Darryl Tschirhart

New ZVS Phase Shift Modulated Full-Bridge Converter Topologies With Adaptive Energy Storage for SOFC Application

This paper presents a new family of zero-voltage switching phase-shift-modulated dc-dc converters for a solid oxide fuel cell application. The proposed converters use a new technique of adaptive energy storage to minimize auxiliary circulating currents for all line and load conditions, thereby maximizing efficiency. A thorough analysis of the proposed topology, including the effects of rectifier junction capacitance, is conducted; and a design procedure presented. Experimental results from a 300 W per bridge, 20 V/300 V prototype are presented to validate the analysis. When compared to a widely used reference topology, the proposed topologies exhibit an efficiency improvement of 7% at full-load.

A CLL Resonant Asymmetrical Pulsewidth-Modulated Converter With Improved Efficiency

In this paper, a CLL resonant tank fed by an asymmetrical pulsewidth-modulated (APWM) drive train is presented as an attractive option for low-power point-of-use power supplies used in telecom applications. This configuration can guarantee zero-voltage switching (ZVS) for an extended input voltage range of 35-75 V, while significantly reducing the associated conduction loss present in existing topologies. Proper resonant tank design will ensure efficient operation over the entire working range by maintaining ZVS for all line and load conditions, as well as minimizing the conduction loss by decreasing the circulating-current commensurate with load. Analysis of the converter topology is conducted, and a design procedure is presented. Experimental results from a 25-W 48-V/2.5-V proof-of-concept prototype are presented to validate the analysis and simulation results and to highlight the merits of the proposed topology. The proposed converter is shown to provide a 7%-14% efficiency improvement over a reference topology.

Design Procedure for High-Frequency Operation of the Modified Series-Resonant APWM Converter to Reduce Size and Circulating Current

In this paper, a generalized analysis for the auxiliary network in a modified series-resonant asymmetrical pulse-width-modulated (APWM) converter is performed to produce a design procedure that ensures that zero voltage switching (ZVS) is achieved for any series-resonant APWM converter design. New equations that correctly predict the magnitude of auxiliary current are obtained by accounting for the trapezoidal nature of the waveforms associated with high-frequency operation, and the dead time between the switches in the half-bridge. A design example of a 48-V/1.2-V, 25-A converter operating at 1 MHz is chosen to highlight the validity of the proposed design and that superior results can be achieved if the resonant tank is designed in tandem with the auxiliary network. Experimental results verify that ZVS is achieved, and that the proposed design reduces the auxiliary inductor by close to a factor of 3.

Secondary-side control of a constant frequency series resonant converter using dual-edge PWM

48V Voltage regulators (VR) can be used to improve the system efficiency of telecom and data centres by eliminating a converter stage in intermediate bus architectures. Small size and improved transient performance can be achieved through high switching frequency if resonant converters are adopted for these applications. This work proposes the use of a dual-edge PWM controller on the secondary-side of a series resonant converter to remove the opto-coupler from the feedback loop, and allow the achievement of fast dynamic performance. Simulation results of a 4MHz 48V/1.2V, 25A example highlight the fast load transient results achievable with standard linear control.

Variable frequency pulse density modulation for efficient high frequency operation of series resonant converters operating as voltage regulators

Voltage regulators (VRs) powering microprocessors face stringent requirements on size; response; and efficiency. Presently, buck converters are used exclusively as VRs for their simple, well-understood behaviour despite their many shortfalls; while more suitable resonant converters are overlooked due to size and performance issues associated with their control methods. In this paper, variable frequency pulse density modulation (VF-PDM) control of the series resonant converter (SRC) is presented to enable resonant converter benefits to be realized in VR applications. It achieves efficient multimegahertz switching frequency, ultra-fast transient response with minimal filter capacitance, and is inherently stable. It will be shown that the SRC under VF-PDM can outperform a two phase buck converter in every aspect including size, speed, and efficiency.

A Cost-Effective Synchronous Rectifier Gating Signal Scheme for Constant Frequency Resonant Converters

In this paper, a novel gating signal scheme for synchronous rectifiers used in constant frequency current-type resonant converters is presented. The advantage of the presented circuit is its low component count when implemented with discrete components, and its ability to be fabricated as an integrated circuit. The gating scheme were derived based on analytical and experimental waveforms from a CLL resonant asymmetric pulse-width-modulated (APWM) converter. The schematic of the logic blocks required to implement the circuit were presented, along with experimental results to prove its legitimacy

Design procedure for high frequency operation of the modified series resonant APWM converter with improved efficiency and reduced size

In this paper, a generalized analysis for the auxiliary network in a modified series resonant asymmetrical pulse-width-modulated (APWM) converter is performed to produce a design procedure that ensures ZVS is achieved for any converter design. New equations that correctly predict the magnitude of auxiliary current are obtained by accounting for the trapezoidal nature of the waveforms associated with high frequency operation, and the dead time between the switches in the half bridge. A design example of a 48V/1.2V, 25A converter operating at 1MHz is chosen to highlight the validity of the proposed design and that superior results can be achieved if the resonant tank is designed in tandem with the auxiliary network. Experimental results verify that ZVS is achieved, and that the proposed design reduces the auxiliary inductor by close to a factor of 3.

A constant frequency series-parallel resonant converter with dual-edge PWM to implement secondary-side control

48V Voltage regulators (VR) can be used to improve the system efficiency of telecom and data centres by eliminating a converter stage in intermediate bus architectures. By adopting resonant converters to implement the 48V VRs, small size, and improved transient performance can be achieved through high switching frequency. This work proposes the use of dual-edge PWM secondary-side control of a series-parallel resonant converter operating at a constant 4MHz to provide 30W at 1.2V from a 48V input. This control method eliminates the opto-coupler from the control loop in applications with isolation requirements; and achieves fast dynamic performance through standard linear control, without the use of a current sensor.

Mixed Signal Synchronous Rectification Scheme for Current-type Resonant Converters

Timing of synchronous rectifier (SR) gating signals for resonant converters in low voltage applications is of paramount importance if high efficiency is to be maintained. Further, to operate at frequencies in the megahertz range, the problems associated with layout parasitics, and individual integrated circuit (IC) delays must be mitigated. Power application specific integrated circuits (PASICs) overcome the aforementioned problems leading to improved performance, minimized component count, and a physically smaller converter. In this paper, a synchronous rectifier logic scheme for current- type resonant converters suitable for PASIC implementation is presented. Through simulation results, it will be shown that the proposed circuit minimizes diode conduction, and provides shoot-through protection to offer an efficient, reliable solution.

Performance of ADC for use in mixed-signal control of synchronous rectifiers in current-type resonant converters

Timing of synchronous rectifier (SR) gating signals for resonant converters in low voltage applications is of paramount importance if high efficiency is to be maintained. Further, to operate at frequencies in the megahertz range, the problems associated with layout parasitics, and individual integrated circuit (IC) delays must be mitigated through the implementation of Power application specific integrated circuits (PASICs). In this paper, a mixed-signal SR control scheme suitable for PASIC implementation is presented as the basis for designing a threshold inverter quantization (TIQ) flash analog-digital converter (ADC). The operation and design of a TIQ flash ADC is reviewed, and compared to a standard flash ADC. Simulated and analytical results comparing area and power consumption metrics of the flash topologies is presented to merit the use of a TIQ ADC in the SR PASIC design.