Dave B. Minturn

ETA: experience with an Intel Xeon processor as a packet processing engine

Server-based networks have well-documented performance limitations. These limitations outline a major goal of Intels embedded transport acceleration (ETA) project, the ability to deliver high-performance server communication and I/O over standard Ethernet and transmission control protocol/Internet protocol (TCP/IP) networks. By developing this capability, Intel hopes to take advantage of the large knowledge base and ubiquity of these standard technologies. With the advent of 10 gigabit Ethernet, these standards promise to provide the bandwidth required of the most demanding server applications. We use the term packet processing engine (PPE) as a generic term for the computing and memory resources necessary for communication-centric processing. Such PPEs have certain desirable attributes; the ETA project focuses on developing PPEs with such attributes, which include scalability, extensibility, and programmability. General-purpose processors, such as the Intel Xeon in our prototype, are extensible and programmable by definition. Our results show that software partitioning can significantly increase the overall communication performance of a standard multiprocessor server. Specifically, partitioning the packet processing onto a dedicated set of compute resources allows for optimizations that are otherwise impossible when time sharing the same compute resources with the operating system and applications.

An architecture for software-based iSCSI on multiprocessor servers

To achieve IP-converged cluster deployments, the performance and scalability of iSCSI must approach that of FC SANs. We recognize and quantify that the major overhead of iSCSI comes from TCP/IP processing. Industry has largely responded with TCP offload engines (TOEs) and iSCSI storage adapters. As an alternative, this paper shows a software implementation of iSCSI on generic OSes and processors. The trend towards chip multiprocessing (CMP) and integrated memory controllers (MCH) largely motivated our direction. With CMP, increased processing power is delivered through multiple cores per processor; on-die MCH allows memory bandwidth to scale better with processor speeds. Our approach and analysis shows the effectiveness of partitioning the workload suitable for a CMP system, allowing iSCSI to scale with the increasing processing power and memory bandwidth of servers over time.

An architecture for software-based iSCSI: experiences and analyses

Supporting multi-gigabit/s of iSCSI over TCP can quickly saturate the processing abilities of a SMP server today. Legacy OS designs and APIs are not designed for the multi-gigabit IO speeds. Most of industrys efforts had been focused on offloading the extra processing and memory load to the network adapter (NIC). As an alternative, this paper shows a software implementation of iSCSI on generic OSes and processors. We discuss an asymmetric multiprocessing (AMP) architecture, where one of the processors is dedicated to serve as a TCP engine. The original purpose of our prototype was to leverage the flexibility and tools available in generic systems for extensive analyses of iSCSI. As work proceeded, we quickly realized the viability of generic processors to meet iSCSI requirements. Looking ahead to chip-multiprocessing, where multiple cores reside on each processor, understanding partitioning of work and scaling to cores will be important in future server platforms.