David A. Kaplan

Bobcat: AMD's Low-Power x86 Processor

Bobcat is an AMD processor core designed for the low-power, mobile, lower-end desktop x86 markets. This core should push current technology in many areas while balancing performance, area, and power consumption. Bobcat supports the 64-bit AMD64 ISA, various SIMD extensions, and a full virtual machine implementation. Bobcat is featured on the AMD Fusion processor family roadmap alongside vector-based parallel processing units in accelerated processing unit configurations.

The SMM Rootkit Revisited: Fun with USB

System Management Mode (SMM) in x86 has enabled a new class of malware with incredible power to control physical hardware that is virtually impossible to detect by the host operating system. Previous SMM root kits have only scratched the surface by modifying kernel data structures and trapping on I/O registers to implement PS/2 key loggers. In this paper, we present new SMM-based malware that hijacks Universal Serial Bus (USB) host controllers to intercept USB events. This enables SMM root kits to control USB devices directly without ever permitting the OS kernel to receive USB-related hardware interrupts. Using this approach, we created a proof-of-concept USB key logger that is also more difficult to detect than prior SMM-based key loggers that are triggered on OS actions like port I/O. We also propose additional extensions to this technique and methods to prevent and mitigate such attacks.

The core-C6 (CC6) sleep state of the AMD bobcat x86 microprocessor

This paper describes the architecture and physical design of the AMD Bobcat x86 microprocessor core-C6 (CC6) sleep state. Each core and dedicated 512KB L2 cache use control flows to save and restore the x86 architectural state in concert with a network of PFET sleep transistors that drive an internal voltage domain. Measured results show an approximate 92% reduction in leakage power at the cost of 1-3% die area with a 31μs restore latency. Each core and L2 cache pair use 98cm of total sleep transistor width in a TSMC 40nm bulk CMOS process.