David Akopian

Architecture-oriented regular algorithms for discrete sine and cosine transforms

We propose fast algorithms for a class of trigonometric transforms. These algorithms have a unified structure and simple data exchange similar to the constant geometry Pease (1968) algorithm derived from the Cooley-Tukey (1965) FFT. We can easily extend many of the parallel FFT approaches for these algorithms. The idea of the method is to localize the nonregularities peculiar to fast algorithms for other trigonometric transforms into the nodes of the Cooley-Tukey FFT type computational graph. Only the basic operation in the nodes of the computational graph will be different for different transforms. Thus, a simple programmable processor element for executing the node functions can be the basis for parallel constructs.

Constant geometry algorithm for discrete cosine transform

Modification to the architecture-oriented fast algorithm for discrete cosine transform of type II from Astola and Akopian (see ibid., vol.47, no.4, p.1109-24, April 1999) is presented, which results in a constant geometry algorithm with simplified parameterized node structure. Although the proposed algorithm does not reach the theoretical lower bound for the number of multiplications, the algorithm possesses the regular structure of the Cooley-Tukey FFT algorithms. Therefore, the FFT implementation principles can also be applied to the discrete cosine transform.

A Wavelet-Denoising Approach Using Polynomial Threshold Operators

This letter presents a new class of polynomial threshold operators for denoising signals using wavelet transforms. The operators are parameterized to include classical soft-and hard-thresholding operators and have many degrees of freedom to optimally suppress undesired noise and preserve signal details. To avoid the complicated process of signal model identification for specific type of signals, a least squares optimization method is proposed for the polynomial coefficients. Our study shows that the proposed term-by-term, fixed-threshold operator can perform as well as adaptively applied, scale-dependent soft and hard thresholding approaches.

Lossless Adaptive Digital Audio Steganography

This paper presents a lossless adaptive digital audio steganographic technique based on reversible two and higher dimensional integer transform. The adaptive technique is used to choose the best blocks for embedding perceptually inaudible stego information, and to select the best block sizes to maximize the number of blocks/capacity. The stego information is embedded in the integer domain by bit manipulation. In addition, we intro- duce a capacity measure to select audio carriers that in- troduce minimum distortion after embedding. The above technique is also applicable to compression based audio formats, such as MPEG audio layer-3 (mp3).

Facilitating Remote Laboratory Deployments Using a Relay Gateway Server Architecture

Hands-on experiments prepare students to deal with real-world problems and help to efficiently digest theoretical concepts and relate those to practical tasks. However, shortage of equipment, high costs, and the lack of human resources for laboratory maintenance and assistance decrease the implementation capacity of the hands-on training laboratories. At the same time, the Internet has become a common networking medium and is increasingly used to enhance education and training. In addition, experimental equipment at many sites is typically underutilized. Thus, remote laboratories accessible through the Internet can resolve cost and access constraints as they can be used at flexible times and from various locations. While many solutions have been proposed so far, this paper addresses an important issue of facilitating remote lab deployments by providing remote connectivity services to lab providers using a Relay Gateway Server architecture. A proof-of-concept solution is described which also includes other previously reported useful features. The system has been tested in engineering labs and student assessment is provided.

Processors for generalized stack filters

New processor structures for generalized stack filters are proposed. They can be implemented using different numbers of Boolean function units. The class of pipeline-parallel structures for generalized stack filters is simple and modular in structure, and suitable for VLSI implementation. Coder and decoder networks are developed for the mutual transform of binary-weighted and unary-weighted codes as the thresholding and addition units of the processors. The area time complexity A/spl middot/T of the proposed filters is O(k/sup 3/) due to the feedback, instead of O(2/sup k/) for the threshold decomposition structure, where k is the number of bits for sample representation. >

A Fast Positioning Method Without Navigation Data Decoding for Assisted GPS Receivers

This paper describes an assisted positioning approach for Global Positioning System (GPS) receivers without navigation data extraction from the received signals. In the presented approach, pseudorange values are reconstructed from partially available measurements, as opposed to conventional techniques, and five or more satellites are used for position computation. The technique is based on iterative estimations of satellite times of transmissions, receiver time, and position using a least-squares method. It is computationally similar to conventional GPS positioning algorithms, but the time to first fix is reduced as there is no need to recover the time of week from navigation data.

A network aided iterated LS method for GPS positioning and time recovery without navigation message decoding

The paper suggests a network aided iterated least squares (LS) method for GPS positioning and time recovery when a navigation message from satellite vehicles (SV) is not available. Using an additional variable which defines the satellite positions, the estimates of time of transmissions and pseudoranges are obtained from measurements available from the tracking side of the receiver. LS iterations are modified to account for adjustment of SV positions on orbits, adjustment of pseudoranges, etc. As a result, the positioning is performed without time-of-week (TOW) information from the navigation message.

Modern WLAN Fingerprinting Indoor Positioning Methods and Deployment Challenges

Wireless local area networks (WLANs) have become a promising choice for indoor positioning as the only existing and established infrastructure, to localize the mobile and stationary users indoors. However, since WLANs have been initially designed for wireless networking and not positioning, the localization task based on WLAN signals has several challenges. Amongst the WLAN positioning methods, WLAN fingerprinting localization has recently garnered great attention due to its promising performance. Notwithstanding, WLAN fingerprinting faces several challenges and hence, in this paper, our goal is to overview these challenges and corresponding state-of-the-art solutions. This paper consists of three main parts: 1) conventional localization schemes; 2) state-of-the-art approaches; and 3) practical deployment challenges. Since all proposed methods in the WLAN literature have been conducted and tested in different settings, the reported results are not readily comparable. So, we compare some of the representative localization schemes in a single real environment and assess their localization accuracy, positioning error statistics, and complexity. Our results depict illustrative evaluation of the approaches in the literature and guide to future improvement opportunities.

Multistage interconnection networks for parallel Viterbi decoders

We propose new multistage interconnection networks (MIN) for scalable parallel Viterbi decoder architectures. The architecture consists of the desired number of processing elements (PE) connected by the suggested MINs, thus allowing a tradeoff between complexity and speed. The structure of the MIN is derived first by transforming the de Bruijn interconnection-based Viterbi algorithm trellis into the equivalent trellis with a perfect shuffle interconnection, and then applying a new decomposition of the perfect shuffle operator. This results in an efficient modular system and data flow is formed by the shuffling in a local PE memory and data exchange through a fixed interconnection between PEs. We suggest several solutions for 1/n and k/n rate codes, where k denotes the number of input bits shifting into k shift registers of the encoder and, at each cycle, the encoder produces n output bits as linear combinations of certain bits in the shift registers.