David B. Chester

Digital IF filter technology for 3G systems: an introduction

Contemporary digital communication systems such as those being developed for the deployment of third-generation cellular require ever increasing performance levels in their signal processing chains to extract higher data rates and to provide decreasing price/performance ratios. Additionally, communication systems like 3G that must support multimode flexibility, such as the software radio, must be able to reconfigure their signal processing chains while keeping circuit complexity to a minimum. Given these constraints, DSP is the only viable alternative for baseband processing and digital IF processing. DSP is in many cases the only viable alternative to analog IF processing. Digital IF affords greater flexibility and higher performance in terms of attenuation and selectivity. It also offers better time and environment stability and lower equipment production costs than traditional analog techniques.

VLSI implementation of a wide band, high dynamic range digital drop receiver

The authors discuss the VLSI implementation of a wideband high-dynamic-range digital drop receiver (DDR) in a three-chip set. The chip set is composed of one numerically controlled oscillator/modulator (NCOM) followed by two decimating digital filters (DDFs). A 16 bit real or 32 bit complex sampled data sequence is input into the NCOM at up to 33 megasamples per second. The NCOM performs a tunable complex down-conversion with greater than 90 dB of spurious-free dynamic range and 0.007 Hz accuracy. The real and imaginary output of the NCOM are each sent to a DDF where they are low-pass-filtered with a stop-band attenuation of up to 120 dB and decimated by up to a factor of 16384. The filter characteristics are fully programmable.<<ETX>>

The wigner distribution in speech processing applications

Abstract Recently the Wigner distribution has been shown to be a potentially useful tool for analysing the time varying frequency domain phenomenon. In this paper, some of the salient features of the Wigner distribution are presented; properties of this important discrete distribution are derived, and an efficient digital implementation is presented. Effective Wigner throughput rates, in excess of those obtainable with an equivalent length FFT, are shown to be feasible. In particular, the Wigner distribution is studied in the context of enhancing speech analysis and recognition systems. It is suggested that this class of distribution is consistent with the mechanics of human speech and, using experimentation, produces a very robust spectral signature. This enriched data space can be used to uncover some frequency domain attributes of human speech which may be lost using a discrete Fourier transform.

Single chip digital down converter architecture

The architecture and algorithmic advancements of the Harris HSP50016 digital downconverter (DDC) are described. The DDC is a fully programmable single-chip downconverter designed to perform intermediate frequency (IF) to baseband processing for communications signal processing. The operation and specification of each major function within the DDC are described, and justification for key specifications is given. The end-to-end performance of the DDC is shown, and the methodology used for measuring the performance is explained.<<ETX>>

High-decimation digital filters

The architecture of an efficient high-decimation rate filter is presented. A high-decimation rate filter can extract narrowband signal intelligence from a wideband signal. As a result, it is important to many signal processing applications found in communications and instrumentation. The presented high-decimation rate filter is a multi-rate system consisting of a cascaded integrator-comb (CIC) section and a finite impulse response (FIR) filter. The function of the CIC section is to perform efficient high-decimation filtering over the entire frequency band. The function of the FIR filter is to achieve prespecified transition band performance at baseband. The authors investigate the CMOS implementation of a 33 MHz high-decimation rate filter, its hardware implementation, and its performance. Examples of its use are also provided.<<ETX>>

Analog to digital converter requirements and implementations for narrowband channelization applications

The processing speeds and dynamic ranges of digital narrowband channelizing devices such as fast Fourier transforms (FFTs) and digital downconverters are far ahead of current analog-to-digital (A/D) converter technology. This would seem to limit the usefulness of these digital devices in real-time applications. Analog preprocessing combined with the digital postprocessing can reduce the limitations of A/D converters in these applications. A detailed examination of A/D converter requirements and limitations in these applications is presented. Preprocessing and postprocessing methods which enhance the performance of the A/D converters are presented. These methods can reduce the impact of the A/D converter as a system bottleneck. Communication system applications are emphasized.<<ETX>>

Modeling of jitter and its effects on time interleaved ADC conversion

Post analog-to-digital conversion correction is an active area of research in both academia and industry due to the high potential of positive impact in areas like Synthetic Instrumentation (SI), Software Defined Radio (SDR), RADAR, etc. This paper introduces a high fidelity Simulink™ based behavioral error model for time-interleaved analog-to-digital converters (TI-ADCs) to facilitate development of efficient post conversion correction algorithms for TI-ADCs. Theoretically TI-ADCs offer a technologically feasible and cost effective solution to the digitization of wide bandwidth analog signals. The contribution of the error model described in this paper solves a key obstacle in economical research and development in this area. In addition to the error sources associated with integrated high performance analog to digital converters ADCs, mismatched error sources affect the performance of time interleaved configurations.

A fully systolic adaptive filter implementation

The authors describe the algorithmic and architectural structure of a representative case of the Harris Semiconductor systolic LMS (least mean square) implementations. Comparison of the systolic and standard transversal LMS implementations of an adaptive filter are given. All of the architectures have a common structure: a systolic tap weight update section followed by a systolic FIR (finite impulse response) filter section. The key to these architectures is a modified coefficient update methodology which facilitates the interface between the two sections. The effects of this methodology are presented. Simulations have shown that the convergence of the systolic filters is comparable to that of the transversal filter for a wide range of filter parameters.<<ETX>>

Featureless chaotic spread spectrum modulation of arbitrary data constellations

Chaotic spread spectrum communication systems provide a number of advantages for secure communications due to the apparent randomness of the underlying spreading signal. Many of these chaotic signals exhibit colored spectra, providing discernible features that enable their detection independent of the transmitted data. A recent digital chaotic circuit [1] has been shown to exhibit a truly white spectrum in addition to apparent time-domain randomness. This maximal entropy characteristic supports Shannons criteria for maximal channel capacity communication, low probability of interception/ detection (LPI/LPD), and a compact bandlimited white spectrum. Such a signal is featureless, susceptible only by energy detection. The disadvantage of such spread communication systems, one shared equally by all spread spectrum systems, is that the channel capacity is constrained by the bandwidth increases required for spreading gain. A traditional approach to increasing bandwidth efficiency is generalizing the modulated digital signaling constellation to include multiple levels of amplitude and phase modulation, which enhances exploitable cyclostationary features unless compensated. This paper presents a framework for adapting the maximal entropy digital chaotic signal to featureless chaotic spread spectrum modulation of arbitrary discrete-time discrete-amplitude data constellations, permitting higher throughputs in chaotic spread spectrum communication systems without sacrificing any of the maximum entropy characteristics that provide LPI/LPD.

Simulink modeling of analog to digital converters for post conversion correction development and evaluation

Theoretically time interleaved analog-to-digital converters (TI-ADCs) offer a technologically feasible and cost effective solution to the digitization of wide bandwidth analog signals. In addition to the error sources associated with integrated high performance analog to digital converters (ADCs) and the exaggerated impact of certain error sources, mismatched error sources exist. The topic of post conversion correction is an active area of research in both academia and industry due to the high potential of positive impact in areas like test instrumentation, software defined radio, radar, etc. A key stumbling block to cost effective research and development is the availability of high fidelity, high level simulations of realistic error performance of data converters. This paper describes a high fidelity, high level Simulink™ based M TI-ADC model capable of facilitating cost effective development of efficient post conversion correction algorithms. Four TI-ADCs are interleaved as an example and errors effects are discussed. A survey of published adaptive correction methods to be evaluated against this model is presented.