David B. Janes

Indium selenide nanowire phase-change memory

Nonvolatile memory device using indium selenide nanowire as programmable resistive element was fabricated and its resistive switching property was studied as functions of electrical pulse width and voltage magnitude. The nanowire memory can be repeatedly switched between high-resistance (∼1011Ω) and low-resistance (∼6×105Ω) states which are attributed to amorphous and crystalline states, respectively. Once set to a specific state, the nanowire resistance is stable as measured at voltages up to 2V. This observation suggests that the nanowire can be programed into two distinct states with a large on-off resistance ratio of ∼105 with significant potential for nonvolatile information storage.

High performance ZnO nanowire field effect transistors with organic gate nanodielectrics: effects of metal contacts and ozone treatment

High performance ZnO nanowire field effect transistors (NW-FETs) were fabricated using a nanoscopic self-assembled organic gate insulator and characterized in terms of conventional device performance metrics. To optimize device performance and understand the effects of interface properties, devices were fabricated with both Al and Au/Ti source/drain contacts, and device electrical properties were characterized following annealing and ozone treatment. Ozone-treated single ZnO NW-FETs with Al contacts exhibited an on-current (Ion) of ~4 µA at 0.9 Vgs and 1.0 Vds, a threshold voltage (Vth) of 0.2 V, a subthreshold slope (S) of ~130 mV/decade, an on–off current ratio (Ion:Ioff) of ~107, and a field effect mobility (μeff) of ~1175 cm2 V−1 s−1. In addition, ozone-treated ZnO NW-FETs consistently retained the enhanced device performance metrics after SiO2 passivation. A 2D device simulation was performed to explain the enhanced device performance in terms of changes in interfacial trap and fixed charge densities.

Gold surface with sub-nm roughness realized by evaporation on a molecular adhesion monolayer

This letter describes a technique for realizing a gold (Au) surface with roughness at the atomic scale using techniques compatible with integrated device fabrication. The Au layer is electron-beam evaporated on a self-assembled monolayer of (3-Mercaptopropyl) trimethoxysilane on an oxidized silicon substrate and shows a root-mean-square surface roughness of ∼2A over a 1μm2 area. The physical stability of the Au film toward commonly used chemicals and processes for photolithography and self-assembly, and its suitability for formation of well-ordered organic monolayers indicate that the films are well suited as substrates for future device fabrication in molecular electronics or other devices involving self-assembled monolayers.

Fully Transparent Thin-Film Transistors Based on Aligned Carbon Nanotube Arrays and Indium Tin Oxide Electrodes†

Adv. Mater. 2008, 20, 1–5 2008 WILEY-VCH Verlag Gmb The development of mechanically flexible and/or optically transparent electronics could enable next-generation electronics technologies, which would be easy-to-read, light-weight, unbreakable, transparent, and flexible. Potential applications could include transparent monitors, heads-up displays, and conformable products. Recent reports have demonstrated transparent thin film transistors (TFTs) using channels consisting of semiconductor nanowires (ZnO, SnO2, or In2O3) and random networks of single-walled carbon nanotubes (SWNTs). Transparent TFTs are attractive for the drive circuitry in transparent and/or flexible active matrix display devices. These devices could overcome the limitations of conventional polycrystalline silicon and amorphous silicon thin film transistors, such as low mobility, nontransparency, or high temperature processing. Among these nanowire and nanotube materials, SWNTs could be a strong candidate for integrating high performance transistor circuits while satisfying the requirements for high density nanoscale integration, including ballistic transport, low power consumption, mechanical flexibility, and optical transparency. SWNT field effect transistors (FETs) using Pd source/drain electrodes and high-k atomic layer deposition (ALD)-based ZrO2 and HfO2 thin films as gate dielectrics have exhibited high performance transistor characteristics, including near ballistic transport and near ideal values of subthreshold slope (S) of 60mV/decade in non-hydrogen ambient conditions. Even though SWNT-FETs provide excellent electrical properties, the integration of individual SWNTs has been impeded by uncontrolled variations of SWNT-TFTs, such as variation of chirality and diameter of SWNTs during thermal chemical vapor deposition (CVD) growth, and alignment for device integration. In order to overcome these limits, new approaches for realization of complex circuits have been demonstrated using well-aligned SWNTarrays on insulating substrates, where the average number of assembled nanotubes are uniform from device to device. Previous studies involving SWNT networks and other semiconductors have demonstrated highly bendable, transparent TFTs, but the network-based TFTs suffer from relatively low mobility and difficulties in scaling down the channel length, making it difficult to obtain high performance transistors. Here, we report the first demonstration of fully transparent TFTs based on well-aligned SWNTs arrays, with conduction from source to drain occurring through individual SWNTs, rather than through networks. A recently developed technique for realizing aligned SWNT arrays on quartz substrates is utilized to place SWNTs into a specific area for the active channel layer. Transparent indium tin oxide (ITO) source/drain and gate electrodes provide excellent contacts to the SWNTs, resulting in high performance transistor characteristics. Representative SWNT-TFTs exhibit high performance depletion-mode p-type transistor characteristics with 83% transparency over the visible wavelength range. The fully transparent SWNT-TFTs could be attractive candidates for future flexible and/or transparent electronics. Figure 1a shows a cross-sectional view of a SWNT-TFT, which employs an aligned array of SWNTs as the active channel, ITO gate, and source/drain electrodes, and a HfO2 gate dielectric. Prior to growth of SWNTs, a ST-cut quartz substrate is annealed for 8 h at 900 8C in air. SWNTs are synthesized on the annealed quartz substrates by thermal CVD of methane using an iron catalyst. Nearly perfect alignment of SWNTs is achieved with direct growth of nanotubes (Fig. 1b). The insert in Figure 1b is a higher-magnification field emission scanning electron microscopy (FESEM) image, showing the well-aligned SWNTs. The parallel arrays of grown SWNT have diameters of 1–5 nm, and an average density of 0.5 tubes mm . The quality of the array could potentially be improved by increasing the annealing time, which might increase the degree of the order in the crystal lattice near the surface. The separation of individual SWNTs in the aligned array avoids junctions within the array, as well as electrostatic screening of the gate field by adjacent SWNTs, resulting in conductance properties per SWNT comparable to studies involving single SWNTs per device. This is a significant improvement over previous reported results on random network SWNT transistors. After depositing ITO source/drain electrodes (100 nm) by ion-assisted deposition (IAD) at room temperature, the electrical burning described below is performed

Nanometer scale electrode separation (nanogap) using electromigration at room temperature

Pairs of electrodes with nanometer separation (nanogap) are achieved through an electromigration-induced break-junction (EIBJ) technique at room temperature. Lithographically defined gold (Au) wires are formed by e-beam evaporation over oxide-coated silicon substrates silanized with (3-Mercaptopropyl)trimethoxysilane (MPTMS) and then subjected to electromigration at room temperature to create a nanometer scale gap between the two newly formed Au electrodes. The MPTMS is an efficient adhesive monolayer between SiO/sub 2/ and Au. Although the Au wires are initially 2 /spl mu/m wide, gaps with length /spl sim/1 nm and width /spl sim/5 nm are observed after breaking and imaging through a field effect scanning electron microscope. This technique eliminates the presence of any residual metal interlink in the adhesion layer (chromium or titanium for Au deposition over SiO/sub 2/) after breaking the gold wire, and it is much easier to implement than the commonly used low-temperature EIBJ technique which needs to be executed at 4.2 K. Metal-molecule-metal structures with symmetrical metal-molecule contacts at both ends of the molecule are fabricated by forming a self-assembled monolayer of -dithiol molecules between the EIBJ-created Au electrodes with nanometer separation. Electrical conduction through single molecules of 1,4-Benzenedimethanethiol (XYL) is tested using the Au/XYL/Au structure with chemisorbed gold-sulfur coupling at both contacts.

1∕f noise of SnO2 nanowire transistors

The low frequency (1∕f) noise in single SnO2 nanowire transistors was investigated to access semiconductor-dielectric interface quality. The amplitude of the current noise spectrum (SI) is found to be proportional to Id2 in the transistor operating regime. The extracted Hooge’s constants (αH) are 4.5×10−2 at Vds=0.1V and 5.1×10−2 at Vds=1V, which are in general agreement with our prior studies of nanowire/nanotube transistors characterized in ambient conditions. Furthermore, the effects of interface states and contacts on the noise are also discussed.

Fabrication and characterization of metal-molecule-silicon devices

Metal-molecule-silicon (MMSi) devices have been fabricated, electrically characterized, and analyzed. Molecular layers were grafted to n and p+ silicon by electrochemical reduction of para-substituted aryl-diazonium salts and characterized using standard surface analysis techniques; MMSi devices were then fabricated using traditional silicon (Si) processing methods combined with this surface modification. The measured current-voltage characteristics were strongly dependent on both substrate type and molecular head group. The device behavior was analyzed using a qualitative model considering semiconductor depletion effects and molecular dipole moments and frontier orbital energies.

Device structure for electronic transport through individual molecules using nanoelectrodes

We present a simple and reliable method for making electrical contacts to small organic molecules with thiol endgroups. Nanometer-scale gaps between metallic electrodes have been fabricated by passing a large current through a lithographically-patterned Au-line with appropriate thickness. Under appropriate conditions, the passage of current breaks the Au-line, creating two opposite facing electrodes separated by a gap comparable to the length of small organic molecules. Current-voltage characteristics have been measured both before and after deposition of short organic molecules. The resistance of single 1,4-benzenedithiol and 1,4-bezenedimethanedithiol molecules were found to be 9MΩ and 26MΩ, respectively. The experimental results indicate strong electronic coupling to the contacts and are discussed using a relatively simple model of mesoscopic transport. The use of electrodes formed on an insulating surface by lithography and electromigration provides a stable structure suitable for integrated circuit a...

Effects of bias stress on ZnO nanowire field-effect transistors fabricated with organic gate nanodielectrics

The effects of bias stress (gate stress or drain stress) on nanowire field-effect transistor (NW-FET) stability were investigated as a function of stress bias and stress time. The n-channel NW-FETs used a nanoscopic self-assembled organic gate insulator, and each device contained a single ZnO nanowire. Before stress, the off current is limited by a leakage current in the 1nA range, which increases as the gate to source bias becomes increasingly negative. The devices also exhibited significant changes in threshold voltage (Vth) and off current over 500 repeated measurement sweeps. The leakage current was significantly reduced after gate stress, but not after drain stress. Vth variations observed upon successive bias sweeps for devices following gate stress or drain stress were smaller than the Vth variation of unstressed devices. These observations suggest that gate stress and drain stress modify the ZnO nanowire-gate insulator interface, which can reduce electron trapping at the surface and therefore redu...

Understanding the Impact of Schottky Barriers on the Performance of Narrow Bandgap Nanowire Field Effect Transistors

Semiconductor nanowires have been explored as alternative electronic materials for high performance device applications exhibiting low power consumption specs. Electrical transport in III-V nanowire (NW) field-effect transistors (FETs) is frequently governed by Schottky barriers between the source/drain and the NW channel. Consequently the device performance is greatly impacted by the contacts. Here we present a simple model that explains how ambipolar device characteristics of NW-FETs and in particular the achievable on/off current ratio can be analyzed to gain a detailed idea of (a) the bandgap of the synthesized NWs and (b) the potential performance of various NW materials. In particular, we compare the model with our own transport measurements on InSb and InAs NW-FETs as well as results published by other groups. The analysis confirms excellent agreement with the predictions of the model, highlighting the potential of our approach to understand novel NW based materials and devices and to bridge material development and device applications.