David B. Shu

The Image Understanding Architecture

This paper provides an overview of the Image Understanding Architecture (IUA), a massively parallel, multilevel system for supporting real-time image understanding applications and research in knowledge-based computer vision. The design of the IUA is motivated by considering the architectural requirements for integrated real-time vision in terms of the type of processing element, control of processing, and communication between processing elements.The IUA integrates parallel processors operating simultaneously at three levels of computational granularity in a tightly coupled architecture. Each level of the IUA is a parallel processor that is distinctly different from the other two levels, designed to best meet the processing needs at each of the corresponding levels of abstraction in the interpretation process. Communication between levels takes place via parallel data and control paths. The processing elements within each level can also communicate with each other in parallel, via a different mechanism at each level that is designed to meet the specific communication needs of each level of abstraction.An associative processing paradigm has been utilized as the principle control mechanism at the low and intermediate levels. It provides a simple yet general means of managing massive parallelism, through rapid responses to queries involving partial matches of processor memory to broadcast values. This has been enhanced with hardware operations that provide for global broadcast, local compare, Some/None response, responder count, and single responder select. To demonstrate how the IUA may be used for vision processing, several sample algorithms and a typical interpretation scenario on the IUA are presented.We believe that the IUA represents a major step toward the development of a proper combination of integrated processing power, communication, and control required for real-time computer vision. A proof-of-concept prototype of 1/64th of the IUA is currently being constructed by the University of Massachusetts and Hughes Research Laboratories.

The Gated Interconnection Network for Dynamic Programming

The SIMD character of fine grain cellular architectures presents serious limitations for all but the first levels of image processing performed. Typically, an image is processed to the point where segmentation has occurred and it is now necessary for region dependent analysis. This might begin with simple data dependent operations such as region labeling followed by extraction of primitive symbolic information (area, perimeter, minimum bounding rectangle) and the gathering of other statistics (moments, histograms). Later this processing would be followed by higher level symbolic operations intended to extract features that ultimately would lead to object recognition. In such cases it is necessary to process each region separately in some way. If there were numerous regions in an image, then a purely SIMD architecture would be efficient only to the extent that the region being processed occupies a significant fraction of the image.

Straight-line detection on a gated-connection VLSI network

An efficient parallel processing algorithm for detecting straight lines on a mesh-connected computer enhanced with a gate-connection network (GCN) is presented. The algorithm is composed of a modified Hough transform that projects compressed pixels in parallel in a given direction and a parallel procedure that extracts the beginning and end points of detected lines. Both parts require the flexible communication capabilities of the enhance mesh. The GCN can be used to dynamically reconfigure the interconnections between hundreds of processors. It is shown how the GCN can electrically connect all of the edge pixels on a straight line. For an n*n pixel array, the algorithm can detect all lines in O(log n) time. Initial experimental results obtained using a simulator of the GCN implemented on a very-large-scale integration (VLSI) chip are presented. Though the accuracy of the algorithm depends largely on the assigned threshold values, the authors believe its speed is superior to that of any other Hough-based technique by a factor of at least two orders of magnitude.<<ETX>>

Image understanding architecture and applications

We describe in this chapter how various image-understanding problems can be mapped onto an architecture and associated implementation specifically designed for such problems. This parallel architecture, which has been funded as part of the DARPA Image Understanding Program, provides a hierarchical, heterogeneous structure to support the wide granularity of processing encountered in the image-understanding domain. In addition, it has an associative capability that allows rapid feedback of global and local summary information to facilitate knowledge-directed processing. We present several applications of this architecture, which span a considerable space of potential use.

An overview of architecture research for image understanding at the University of Massachusetts

Architectural research in support of knowledge-based computer vision is described. Efforts are focused on two major areas: the development of the image understanding architecture (IUA) and the benchmarking of parallel processors for vision. Two aspects of the IUA research are discussed. One is the development of the low-level processor chip, which integrates 64 one-bit (serial) processors, data caches, a communication network, and parallel interfaces to image input/output (I/O) hardware and the intermediate-level processors. The other is the ICAP, which is designed to manipulate tokens (symbolic descriptions of extracted image events and their associated attributes) at the intermediate level and to support database functions that allow access to these tokens. Work on an image understanding work bench is briefly described.<<ETX>>

Parallel implementation of image understanding tasks on gated-connection networks

The authors present a summary of research in design and implementation of parallel algorithms for image computing tasks on an enhanced mesh connected computer called Gated-Connection Network (GCN). The GCN allows dynamic reconfiguration of mesh interconnectivity using switches located at the grid points. The flexibility of the GCN leads to significant improvements in time complexity of several image computing tasks. Line detection and finding connected components are some of the problems studied for low and intermediate level processing. Parallel implementation of symbolic computation tasks for image understanding and pattern recognition (e.g. cylinder matching) is another class of problems addressed.<<ETX>>

Heterogeneous algorithms for image understanding architecture

The authors present a set of heterogeneous algorithms for computer vision tasks using the image understanding architecture (IUA). The full-scale IUA developed jointly by Hughes Research Labs and University of Massachusetts at Amherst is a multiple level heterogeneous architecture. Each level is constructed to perform tasks most suitable to its mode of processing. The lowest level called CAAPP is an SIMD bit-serial mesh. The second level is an MIMD organization of numerically powerful digital signal processing chips. At the top level there are fewer number of MIMD general purpose processors. The authors propose a set of algorithms utilizing multiple levels of this organization, concurrently. The problems studied include Hugh transform-line detection, finding geometric properties of images, and high level image understanding tasks such as object matching.