David C. Christian

Development of a pixel readout chip for BTeV

A description is given of the R&D program underway at Fermilab to develop a pixel readout ASIC appropriate for use at the Tevatron collider. Results are presentetd frOm tests performed on the first prototype pixel readout chip deigned at Fermilab, and a new readout architecture is described.

FPIX2: A radiation-hard pixel readout chip for BTeV

A radiation-hard pixel readout chip, FPIX2, is being developed at Fermilab for the recently approved BTeV experiment. Although designed for BTeV, this chip should also be appropriate for use by CDF and DZero. A short review of this development effort is presented. Particular attention is given to the circuit redesign which was made necessary by the decision to implement FPIX2 using a standard deep-submicron CMOS process rather than an explicitly radiation-hard CMOS technology, as originally planned. The results of initial tests of prototype 0.25{micro} CMOS devices are presented, as are plans for the balance of the development effort.

A Vertically Integrated Pixel Readout Device for the Vertex Detector at the International Linear Collider

Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20 × 20 ¿m2 pixels, laid out in an array of 64 × 64 elements and was fabricated in a 3-tier 0.18 ¿m Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout.

PreFPIX2: core architecture and results

PFIX is a pixel architecture designed for colliding-beam experiments at the Tevatron. Its most important application to date is the BTeV experiment. PreFPIX2 is a chip designed to test the FPIX Core, i.e., the pixel control and readout architecture. This FPIX Core will be mated to a periphery specific to a particular experiment. Earlier plans called for the BTeV FPIX chip to be designed in a rad-hard process. However, deep-submicron CMOS processes have demonstrated appropriate radiation tolerance at a lower cost and with greater reliability. Therefore, PreFPIX2 has been fabricated in a 0.25 micrometer process utilizing radiation tolerant design techniques. The architecture has undergone substantial development from earlier versions of FPIX. Most notable are the improvements to the column token passing scheme and to the end-of-column logic. Extensive simulations were performed using both SPICE and structural-level Verilog. Monte Carlo physics simulations of the BTeV pixel detector at half, full and double the planned luminosity were converted to Verilog compatible input files for the chip simulations, allowing the designers to observe the chip operating under real conditions and for extended periods of time. Analyzes of the results reveal that at all luminosities the FPIX Core correctly identifies better than 99.6% of input hits. Bench tests of fabricated chips confirm the accuracy of the simulations.

A high-rate Fastbus silicon strip readout system

A synchronous silicon strip readout system capable of zero dead-time readout at average trigger rates in excess of 1 MHz is described. The system is implemented in Fastbus, uses pipelining techniques, and includes point-to-point fiberoptic data links to transmit detector digital data. Semicustom ASIC (application-specific integrated circuit) chips are used to amplify, discriminate, and logically combine track data before encoding. The overall system, each major Fastbus module, and the functional aspects of the ASIC chips are described. >

Beam test results of the BTeV silicon pixel detector

Abstract The results of the BTeV silicon pixel detector beam test carried out at Fermilab in 1999–2000 are reported. The pixel detector spatial resolution has been studied as a function of track inclination, sensor bias, and readout threshold.

High rate drift chambers

Fermilab experiment 690, a study of target dissociation reactions pp + pX using an 800 GeVlc proton beam and a liquid hydrogen target, collected data in late 1991. The incident beam and 600-800 GeV/c scattered protons were measured using a system of six 6” x 4” and two 15” x 8” pressurized drift chambers spaced over 260 meters. These chambers provided precise measurements at rates above 10 MHz (2 MHz per centimeter of sense wire). The measurement resolution of the smaller chambers was 90 urn, and the resolution of the larger chambers was 125 pm. Construction details and performance results, including radiation damage, are presented.

The development of two ASICs for a fast silicon strip detector readout system

The authors review the design and prototyping of two application specific integrated circuits (ASICs), an amplifier and a discriminator, which are being produced for the Fermilab E771 silicon strip detector readout system. The two bipolar ASICs were designed and prototyped using Tektronix Quickchip 2 linear arrays. Measurements of the performance of the prototype devices are presented that agree very well with the results SPICE simulations. >

Development of high data readout rate pixel module and detector hybridization at Fermilab

This paper describes the baseline design and a variation of the pixel module to handle the data rate required for the BTeV experiment at Fermilab. The present prototype has shown good electrical performance characteristics. Indium bump bonding is proven to be capable of successful fabrication at 50 micron pitch on real detectors. For solder bumps at 50 micron pitch, much better results have been obtained with the fluxless PADS processed detectors. The results are adequate for our needs and our tests have validated it as a viable technology.

Study of indium and solder bumps for the BTeV pixel detector

The pixel detector proposed for the BTeV experiment at the Fermilab Tevatron will use bump-bonding technology based on either Indium or Pb/Sn solder to connect the front-end readout chips to the silicon pixel sensors. We have studied the strength of the bumps by visual inspection of the bumps bonding silicon sensor modules to dummy chips made out of glass. The studies were done before and after thermal cycles, exposed to intense irradiation, and with the assemblies glued to a graphite substrate. We have also carried out studies on effects of temperature changes on both types of bump bonds by observing the responses of single-chip pixel detectors to an Sr/sup 90/ source. We report the results from these studies and our plan to measure the effect of cryogenic temperatures on the bumps.