David Cooperberg

Semiempirical profile simulation of aluminum etching in a Cl2/BCl3 plasma

A semiempirical profile simulator to predict topographic evolution during Cl2/BCl3 plasma etching of photoresist patterned Al lines has been developed. Given incident flux distributions, the profile simulator uses a combination of a particle based Monte Carlo algorithm and analytic ray-tracing algorithm for solving feature-scale ion and neutral flux transport, respectively. We use angular and energy distributions for reflected ions that are consistent with experimental observation and molecular dynamic simulations. Etch yields with energy and angular dependence are experimentally determined for physical sputtering and ion-enhanced etching. The spontaneous etch rate of A1 by chlorine and the spontaneous desorption rate of Cl from photoresist are estimated from experimental results. Sticking coefficients for etchant, chlorine, and depositor, CClx, and depositing flux are determined by fitting simulated profiles to experimental data. A semiempirical site-balance model is developed to compute the surface cove...

Manufacturability considerations in designing optical monitoring methods for control of plasma etch processes

Robustness and reliability are among the most important requirements of semiconductor manufacturing processes. Their importance grows with the need to continuously improve yield and contribute to reduced cost of ownership. This necessitates including manufacturability considerations in the fundamental design of methods and instruments for in situ control of plasma etch processes. Optical monitoring methods and equipment for broadband (UV-VIS-IR) reflectometry have been developed to meet these advanced needs. The hardware is optimized for sufficiently accurate in situ metrology capabilities in a harsh plasma processing environment with minimal maintenance requirements. Novel model-based approaches are used to determine the absolute wafer state in real time. This facilitates compensating for incoming material variation with minimal reliance on operator input and interpretation. No special test structures on the wafer are required while the process chamber is only minimally modified for diagnostic equipment access. The methods facilitate development of fault detection schemes that help prevent misprocessing of wafers. Thus, demanding process control requirements are met on a wafer-to-wafer basis. The applicability of the technique has been successfully demonstrated for critical silicon-based etch applications such as shallow trench isolation (STI), recess for DRAM and embedded DRAM (eDRAM), and polysilicon gate.