David E. Kotecki

Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology

A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. This DDS uses a sine-weighted digital to analog converter (DAC) architecture that eliminates the need for a ROM. This enables operation at high frequencies with lower power consumption compared to traditional approaches. The phase accumulator is 8-bits wide and the sine-weighted DAC uses the five most significant bits (MSBs) for phase to amplitude conversion. The DDS operates up to a 32-GHz clock frequency for all frequency control words (FCWs) and can synthesize sine-wave outputs from 125 MHz to 16GHz in 125-MHz steps. The spurious free dynamic range (SFDR) is measured over the Nyquist bandwidth to be 31.00 dBc for the fundamental output frequency of 125 MHz. Over the full range of FCWs, the worst case SFDR is 21.56 dBc at an FCW of 95, and the average SFDR is 26.95 dBc. The circuit is implemented with 1891 transistors and consumes 9.45 W of power

Direct digital synthesizer with ROM-Less architecture at 13-GHz clock frequency in InP DHBT technology

A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. The DDS has a ROM-less architecture and instead uses digital logic for phase conversion. The DDS operates up to a 13 GHz clock rate and is capable of synthesizing output frequencies up to 6.5 GHz. Measured spurious free dynamic range (SFDR)ranged from 34 dBc at low frequency control words (FCWs) to 26.67 dBc at high FCWs. The test circuit is implemented with 1646 transistors and consumes 5.42W of power

4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

A 41-GHz 4-b adder-accumulator test circuit implemented in InP double heterojunction bipolar transistor (DHBT) technology using 624 transistors is reported. High clock rates are obtained by combining the logic functions into pipelined latches. The adder-accumulator contains a single-level parallel-gated carry circuit that is used as a step toward reduced power consumption. The carry circuit has a maximum clock frequency of 55 GHz. The accumulator architecture employs modular, pipelined 2-b adders and is cascadable to 2 N-bits. The test circuit includes a 4-b digital to analog converter (DAC) that facilitates demonstration of high-speed operation.

36-GHz, 16

A 16times6-bit read-only memory (ROM), employing an architecture suitable for use as a phase to amplitude converter for direct digital synthesizers (DDS), has been implemented in InP double heterojunction bipolar transistor (DHBT) technology. The ROM uses a -3.8 V power supply and dissipates 1.13 W of power. The ROM is implemented in a test circuit that includes an 8-bit accumulator and a 6-bit digital-to-analog converter (DAC) to facilitate demonstration of high-speed operation. The maximum operating clock frequency is measured to be 36 GHz

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The scaling down of on-chip microelectronic capacitors presents a considerable challenge for future microelectronic devices. High-permittivity polycrystalline dielectrics such as Ta/sub 2/O/sub 5/, SrTiO/sub 3/ (STO), or (Ba, Sr)TiO/sub 3/ (BSTO), have been considered as a potential replacement for conventional amorphous SiO/sub 2/ and SiN/sub x/. The polycrystalline microstructure of these materials may lead to capacitor-to-capacitor variations in charge storage capacity and charge retention. In this letter, a Monte Carlo simulation is used to assess these variations. Results show that as the average crystalline grain size becomes greater than 1% of the capacitor size, variations of 10% in capacitance and between 3-150% in leakage should be expected.

6-Bit ROM in InP DHBT Technology Suitable for DDS Application

Nanopore DNA sequencing devices show promise for rapidly decoding genetic information, although single nucleotide detection appears to be beyond the sensitivity of present transmembrane current measurement schemes. In this paper, a nanodevice combining nanoelectrodes with a nanopore was made to measure the nucleotide dependent transverse tunneling currents during the translocation of DNA through the nanopore. A custom high speed, low noise, integrated circuit current amplifier was designed and fabricated to measure the tunneling current. This nanodevice was characterized electrically using 2 nm to 20 nm gold nanoparticles as an artificial construct for DNA using both DC and AC detection schemes. Measured transverse tunneling currents were found to be quantized, probably according to the number of nanoparticles residing within the pore.

Simulation of the variability in microelectronic capacitors having polycrystalline dielectrics

Most of the literature on Ultra Wide Band (UWB) transmitters is focused on indoor communications. This paper presents the architecture of an Impulse Radio Ultra Wide Band (IR-UWB) transmitter for outdoor communications which complies with the FCC spectral limits. The transmitter consists of a pulse generator (PG) and a deriver circuit and has an operating frequency between 3.1 GHz and 6.4 GHz. The pulse output amplitude is ~ 700mV peak-to-peak into a 50Ω resistive load. The maximum data rate that can be achieved by the transmitter is 250Mbps at an overall power efficiency of 6.3%. The transmitter is compensated for voltage and temperature (VT) variations. The output pulse energy changes by less than 24% as the temperature varies from -55°C to 100°C, and by less than 5% as the supply voltage varies between 2.3 and 3.6V. The design is implemented in 180nm CMOS process and the simulation results with extracted R, L, C parasitics are presented.

Nanopore with Transverse Nanoelectrodes for Electrical Characterization and Sequencing of DNA

Wide tuning range voltage-controlled oscillators (VCO) are envisioned for applications in radars, broadband communications, phase-locked loops and clock generation/distribution. In this paper, post-layout simulation results of a combined VCO with a ring quadrature VCO (QVCO), an exclusive-OR (XOR) and a fourth-harmonic summation block in 130nm SiGe BiCMOS technology are presented. The combined VCO can be tuned from 2.9 to 30.3GHz. At 2.9GHz, the VCO consumes 32.89mW of power and generates −56.5 dBm (2.24nW) of output power into a 50 Ohm load. At 30.3GHz, it consumes 34.2mW of power and generates −33.5 dBm (398nW) of output power. In both cases, the XOR consumes ∼25mW of power and the fourth-harmonic block consumes ∼5mW of power. The VCO phase noise at 10MHz offset frequency is −102.2dBc/Hz and −86.04dBc/Hz at 2.9GHz and 30.3GHz, respectively. The VCO figure of merit (FOM) is in the range of −136 to −141. The microchip area is 750µm×500µm. This VCO provides the widest tuning range in the 130nm ring VCOs reported till now.

Temperature and supply voltage insensitive OOK transmitter for UWB outdoor communications

A 3-D microelectronic inductor has been fabricated and characterized for use as a magnetic flux sensor, also known as a telecoil, for a hearing aid application. This telecoil was fabricated in a 0.5 mum CMOS process with three metal layers. The 3-D structure is more space efficient than conventional spiral inductors and allows for an optimal number of turns for the space available. The telecoil has an inductance of 80 muH, a resistance of 34 Omega, and a capacitance of 275pF. When combined with an CMOS audio amplifier, the telecoil acts as a magnetic flux sensor by picking up the magnetic signal generated by telephone speaker which is then fed into the audio amplifier. The integrated telecoil is smaller in size and can be produced at a lower cost than commercially available telecoils. The electrical response of the telecoil to a changing magnetic field was found to be linear with respect to the input amplitude, and neglecting the noise associated at lower frequencies, independent of frequency. This response is in agreement with theory.

A 2.9–30.3GHz fourth-harmonic voltage-controlled oscillator in 130nm SiGe BiCMOS technology

Two 32times6-bit read only memory (ROM) circuits, employing an architecture suitable for use as a phase to amplitude converter for direct digital synthesizers (DDS), have been designed in InP double heterojunction bipolar transistor (DHBT) technology. These ROM designs use a -3.8 V power supply and dissipate 1.95 W and 7.07 W of power respectively. The maximum operating clock frequencies for these designs are simulated to be 20 GHz and 46 GHz respectively.