David Fong | Researchain

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Publication

Featured researches published by David Fong.

Archive | 2003

High density semiconductor memory cell and memory array using a single transistor

Jack Zezhong Peng; David Fong

Archive | 2002

Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric

David Fong; Fei Ye; Jack Zezhong Peng

Archive | 2007

Memory transistor gate oxide stress release and improved reliability

David Fong; Jianguo Wang; Jack Zezhong Peng; Harry Shengwen Luan

Archive | 2005

Combination field programmable gate array allowing dynamic reprogrammability

Jack Zezhong Peng; Zhongshang Liu; David Fong; Fei Ye

Archive | 2007

Electrically programmable fuse bit

Jack Zezhong Peng; David Fong; Glen Arnold Rosendale

Archive | 2004

Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric

Jianguo Wang; David Fong; Jack Zezhong Peng; Fei Ye; Michael David Fliesler

Archive | 2003

Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage

Jack Zezhong Peng; Harry Shengwen Luan; Jianguo Wang; Zhongshan Liu; David Fong; Fei Ye

Archive | 2010

Low voltage and low power memory cell based on nano current voltage divider controlled low voltage sense MOSFET

Jack Zezhong Peng; David Fong

Archive | 2006

Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit

Jack Zezhong Peng; David Fong; Harry Shengwen Luan; Jianguo Wang; Zhongshang Liu

Archive | 2012

SOFT BREAKDOWN MODE, LOW VOLTAGE, LOW POWER ANTIFUSE-BASED NON-VOLATILE MEMORY CELL

Jack Zezhong Peng; David Fong

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Archive Network Publication Hotspot Collaboration

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot

Dive into the research topics where David Fong is active.

Publication

Featured researches published by David Fong.

High density semiconductor memory cell and memory array using a single transistor

Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric

Memory transistor gate oxide stress release and improved reliability

Combination field programmable gate array allowing dynamic reprogrammability

Electrically programmable fuse bit

Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric

Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage

Low voltage and low power memory cell based on nano current voltage divider controlled low voltage sense MOSFET

Memory cell comprising an OTP nonvolatile memory unit and a SRAM unit

SOFT BREAKDOWN MODE, LOW VOLTAGE, LOW POWER ANTIFUSE-BASED NON-VOLATILE MEMORY CELL

Collaboration

Dive into the David Fong's collaboration.