David J. Greaves

Kiwi: Synthesis of FPGA Circuits from Parallel Programs

We describe the Kiwi parallel programming library and its associated synthesis system which is used to transform C# parallel programs into circuits for realization on FPGAs. The Kiwi system is targeted at making reconfigurable computing technology accessible to software engineers that are willing to express their computations as parallel programs. Although there has been much work on compiling sequential C-like programs to hardware by automatically `discovering¿ parallelism, we work by exploiting the parallel architecture communicated by the designer through the choice of parallel and concurrent programming language constructs. Specifically, we describe a system that takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to FPGAs. We can then choose to apply analysis and verification techniques to either the highlevel representation in C# or other .NET languages or to the generated RTL netlists. A distinctive aspect of our approach is the exploitation of existing language constructs for concurrent programming and synchronization which contrasts with other schemes which introduce specialized concurrency control constructs to extend a sequential language.

Communication primitives for ubiquitous systems or RPC considered harmful

RPC is widely used to access and modify remote state. Its procedural call semantics are argued as an efficient unifying paradigm for both local and remote access. Our experience with ubiquitous device control systems has shown otherwise. RPC semantics of a synchronous, blocking invocation on a statically typed interface are overly restrictive, inflexible, and fail to provide an efficient unifying abstraction for accessing and modifying state in ubiquitous systems. This paper considers other alternatives and proposes the use of comvets (conditional, mobility aware events) as the unifying generic communication paradigm for such systems.

Internet access to a home area network

The AutoHan project implements a self-configuring software architecture for home area networks that offers an XML-based registry and HTTP-based service. The article begins by introducing the low-level architectures of the AutoHan project that enable different networking technologies to interoperate and define one logical IP network. It then describes the two core services that enable resources to export, discover and interoperate with AutoHan by using these low-level architectures. Finally, the article discusses naming and addressing issues for Internet access and shows how XML and HTTP allowed extension of the system to support Internet access through IHan (Internet home area network).

The Cambridge Backbone Ring

An experimental ring communication network, the Cambridge Backbone Ring, for integrated computer data, voice, and real-time video applications is described. The network is aimed as a backbone facility for interconnecting groups of Cambridge Fast Ring (CFR) networks in the Cambridge area. Media access control is through the empty slot technique, with transmitting stations filling multiple slots each ring revolution. The network operates on monomode optical fiber and is designed for an eventual line rate of 1000 Mb/s. In the backbone ring architecture, the bandwidth of the fiber-optic channel can be partitioned into a number (currently four) of time division multiplexing (TDM) channels. This enables stations of varying cost and bandwidth to be attached to one network, parameterized by the number of channels a station can use concurrently. The backbone ring architecture achieves full connectivity, even with the simplest type of station. Some brief traffic simulation results are presented.<<ETX>>

TLM POWER3: Power estimation methodology for SystemC TLM 2.0

We report on a SystemC add-on library which extends every SystemC module with non-functional data regarding power consumption and physical layout and which accumulates and estimates dynamic energy usage. It supports both phase/mode power modelling and energy-per-transaction logging for TLM (transactional-level modelling). Wiring energy is computed by counting bit-level activity within the TLM generic payload. Each leaf component can also register its physical dimensions to facilitate a wire length estimator that traverses the SystemC model hierarchy using either full placement or Rents rule estimators. It also supports dynamic voltage islands and inter-chip wiring, where each transaction can consume energy according to the current supply voltage of the relevant islands and the nature of the interconnect. We report on basic peformance from some SPLASH-2 benchmarks running on a modelled OpenRISC quad-core platform.

Control software for home automation, design aspects and position paper

The home is an eternal, heterogeneous, distributed computing environment which must be secure and reliable. Computers and embedded processors in the home are all different shapes and sizes and ages. Hence the home poses one of the most challenging environments for co-operative programming. We envisage that control software is introduced into the home by four different methods varying from embedded ROM code to applets generated from a combination of natural language and gesture with wands. But we argue that, in the long term, all of it must be represented in a common, formally-verifiable language and conform to a common scripting convention. The AutoHan project at the University of Cambridge Computer Laboratory is the umbrella under which we are trying to grow these ideas.

A Verilog to C compiler

This paper describes a compiler which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native-mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics of Verilog, and also performs logic minimisation. Buses of up to 32 or 64 bits can be modelled as C integers, whereas larger buses are automatically split. We describe the motivation, method and quality of the results.

Warren: a low-cost ATM home area network

This article introduces the concept of the ATM Warren. The Warren is an arbitrary mesh subnetwork of very simple ATM switches and end stations connected to the wide-area B-ISDN at one or more points. The Warren differs from other ATM networks in that both switches and end stations are designed to be implemented entirely in hardware with all control software banished to external computers.

Designing application specific circuits with concurrent C# programs

This paper presents an investigation into the possibility of using a regular concurrent programming language for modeling and implementing digital circuits. Some of the reasons for using an existing language include the ability to use existing compilers and analysis tools for circuit design and verification. Another important reason is the ever increasing need to model complete systems that comprise interacting software and hardware in a single framework which facilitates easier migration of sub-components between hardware and software implementations compared to multi-model approaches. To this end we present the design of the Kiwi system which models digital circuits with concurrent programs using a standard library in C# for multi-threaded programming. Kiwi models can be executed using a regular C# compiler. Also, the compiled bytecode can be automatically converted into circuits using our Kiwi hardware synthesis system.

Protocol and Interface for ATM LANs

This paper describes the design and performance of a simple ATM host interface for a RISC workstation together with the MSNA protocol architecture. A feature of the MSNA architecture is that it can provide ATM virtual circuits directly to applications by demultiplexing to a degree normally associated with the transport layer of a protocol stack. We discuss implementations of the ATM adaptation layer of varying complexity and discuss the appropriate place for the adaptation layer to be terminated in a multimedia workstation.