David J. Pritchard

Practical Parallelism using Transputer Arrays

This paper explores methods for extracting parallelism from a wide variety of numerical applications. We investigate communications overheads and load-balancing for networks of transputers. After a discussion of some practical strategies for constructing occam programs, two case studies are analysed in detail.

Monte Carlo Simulation on Transputer Arrays

Abstract A Monte Carlo simulation of a simple statistical physics model is decomposed onto a multi-processor (transputer) array in two essentially different ways: using ‘geometric’ and ‘algorithmic’ concurrency. The geometric decomposition (in which each processor handles a small sector of the physical system) is characterized by high efficiency in utilization of processors, and relative simplicity in programming. The algorithmic decomposition (in which each processor handles a small sub-task of the full algorithm, typically in a pipelined mode) is characterized by greater flexibility in the data-size (size of the physical system) and minimal memory requirements for a majority of the processors in the array. These assertions are made concrete in relation to our specific problem (a two-dimensional spin system simulation) which is, in many respects representative of a wide class of problems of interest to theoretical physicists.

Cube connected Mobius ladders: an inherently deadlock-free fixed degree network

The authors introduce a multiprocessor interconnection network, known as cube-connected Mobius ladders, which has an inherently deadlock-free routing strategy and hence has none of the buffering and computational overhead required by deadlock-avoidance message passing algorithms. The basic network has a diameter phi of 4n-1 for n2/sup n+2 /nodes and has a fixed node degree of 4. The network can be interval routed in two stages and can be represented as a Cayley graph. This is the only practical fixed degree topology of size O(2/sup phi /) which has an inherently deadlock-free routing strategy, making it ideally suited for medium and large sized transputer networks. >

Simulation of Statistical Mechanical Systems on Transputer Arrays

Abstract The INMOS transputer is a powerful VLSI microprocessor that is especially suited for the construction of large arrays for parallel computation. We discuss the general features of such arrays and illustrate these with a simulation of a generalised XY model with possible applications in liquid crystal film modelling.

Portable Parallel Programming Environment - The ESPRIT PPPE Project

Keywords : Parallel performance monitoring, debugging, software engineering, integrated toolset.

Load balanced deadlock-free deterministic routing of arbitrary networks

This paper provides efficient algorithms to deadlock-free route arbitrary multiprocessor interconnection networks as follows: 1. An algorithm is derived for fixed directory routing on an arbitrary network topology such that messages will be routed via one of the shortest routes whilst maintaining an even distribution of traffic over the network (assuming that messages are generated and absorbed in an even manner, or two-phase random routing is used). 2. An algorithm is presented which will evenly map virtual links onto the routed network so that it will be deadlock-free using the minimum number of buffer classes per physical link, thus maximising the buffer size per virtual link.