David K. Probst

Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems

We avoid state explosion in model checking of delay-insensitive VLSI systems by not using states. Systems are networks of communicating finite-state nonsequential processes with well-behaved nondeterministic choice. A specification strategy based on partial orders allows precise description of the branching and recurrence structure of processes. Process behaviors are modelled by pomsets, but (discrete) sets of pomsets with implicit branching structure are replaced by pomtrees, which have finite presentations by (automaton-like) behavior machines. The latter distinguish both concurrency and branching points, and define a finite recurrence structure. Safety and liveness checking are integrated. In contrast to state methods, our methods do not require enumeration or recording of states. We avoid separate consideration of execution sequences that do not differ in their partial order, and ensure termination by recording only a small number of system loop cutpoints — in the form of system behavior states. In spite of the name, behavior states are not states.

Partial-Order Model Checking: A Guide for the Perplexed

Practicing verifiers of finite-state concurrent systems should be able to adapt our partial-order methods for verifying delay-insensitive systems to other verification problems. We answer the question, is it possible to control state explosion arising from various sources during automatic verification (model checking) of delay-insensitive systems? State explosion due to concurrency is handled by introducing a partial-order representation for processes, and defining system correctness as a simple relation between two partial orders on the same set of system events. State explosion due to nondeterminism is handled when the system to be verified has a compact, finite recurrence structure. Backwards branching through representations is a further optimization. In system verification, we start with models of system components that explicitly distinguish concurrency, choice and recurrence structure; during model checking, this a priori structure of components allows us to construct a compact, finite representation of the specification-constrained implementation — without prior composition of system components. The fully-implemented POM verification system has polynomial space and time performance on traditional asynchronous-circuit benchmarks that are exponential in space and time for other verification systems; in general, the cost of running our verification algorithm is proportional to the size of the constructed system representation.

Abstract specification of synchronous data types for VLSI and proving the correctness of systolic network implementations

A combined methodology is presented for specifying abstract synchronous data types and proving the correctness of systolic network implementations. It is shown that an extension of the Parnas trace method of specifying software modules containing distinct access programs yields a natural method of specifying abstract synchronous data types that possess distinct access operators and are intended for implementation in VLSI. Associated systematic proof techniques are presented, and the correctness of several novel systolic network implementations of familiar data types is established. The methodology appears to be naturally suited to systolic network implementations with their associated rippling of control flow and data flow. The important distinction between systolic control-flow networks and systolic data-flow networks is presented. >

Programming, compiling and executing partially-ordered instruction streams on scalable shared-memory multiprocessors

Performance in large-scale shared-memory multiprocessors depends on finding a scalable solution to the memory-latency problem. The author shows that protect consistency (PRC) relaxes previous consistency models with two distinct performance benefits. First, PRC is used to expose and exploit more parallelism in the computation, giving better support to latency tolerance. Second, assuming that visible synchronization directly coordinates changes in the writability of shared data, PRC is used to create more situations where cached data are reusable, giving better support to latency avoidance. The paper evaluates PRC in the context of relaxing intrathread dependences for multithreaded architectures. After the PRC programming notation is described, programming and compiling aspects are examined, and architectural support is discussed.<<ETX>>

Optimal VLSI dictionary machines without compress instructions

Several designs are presented for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The initial design objectives included: (1) single-cycle operability of host-issued modify and query commands (no compress instructions), (2) complete processor utilization (no waste processors), and (3) optimal 2 log n response times, where n is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously. They were forced to abandon objective (3), instead achieving a slightly weaker objective, namely, near-optimal (2 log n+R) response times, where R is the time for a round trip through the particular prenetwork used to connect the host to the roots of the query trees in the logarithmic network. Both sorted and unsorted versions of dictionary machines are presented. Those with orthogonal command networks achieve all objectives; those without orthogonal networks achieve only the first and third. >

A fast, low-space algorithm for multiplying dense multivariate polynomials

This paper presents an improved adaptive hybrid algorithm for multiplying dense multivariate polynomials that is both time and space efficient. The hybrid algorithm makes use of two families of univariate algorithms, one Karatsuba based and the other DFT based, which are applied recursively to solve the multivariate problem. The hybrid algorithm is adaptive in that particular univariate algorithms are selected at run time to minimize the time complexity; an order-of-magnitude speedup with respect to classical multiplication is achieved over the entire practical range except for very small problems. Empirical investigation shows that most of the theoretical superiority is maintained in actual implementation. The largest contribution to the space requirements of the total algorithm is determined by the univariate algorithm used for the outermost variable; except for quite small problems, selecting univariate algorithms to minimize run time almost always leads to situations where the space requirements of the total algorithm are extremely close to the space required merely to store the result.

A Family of Algorithms for Powering Sparse Polynomials

We discuss four new algorithms from a family of algorithms for computing integer powers of sparse polynomials. The four algorithms form a sequence of successively better algorithms; even the first member of the sequence shows an improvement in the leading term of the cost function in comparison with the best previously known binomial-expansion algorithm. To quote one result, if f is a 32-term sparse polynomial, computing

Advances in Hardware Design and Verification

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Modelling Reactive Hardware Processes Using Partial Orders

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Panel Discussion: Is There a Crisis in Hardware Verification?

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