David Kwong

A Sub-1 V, 26

We present a low-power bandgap reference (BGR), functional from sub-1 V to 5 V supply voltage with either a low dropout (LDO) regulator or source follower (SF) output stage, denoted as the LDO or SF mode, in a 0.5-μm standard digital CMOS process with <i>V</i>_tn ≈ 0.6 V and |<i>V</i>_tp| ≈ 0.7 V at 27°C. Both modes operate at sub-1 V under zero load with a power consumption of around 26 μW. At 1 V (1.1 V) supply, the LDO (SF) mode provides an output current up to 1.1 mA (0.35 mA), a load regulation of ±8.5 mV/mA (±33 mV/mA) with approximately 10 μs transient, a line regulation of ±4.2 mV/V ( ±50 μV/V), and a temperature compensated reference voltage of 0.228 V (0.235 V) with a temperature coefficient around 34 ppm/°C from -20°C to 120 °C. At 1.5 V supply, the LDO (SF) mode can further drive up to 9.6 mA (3.2 mA) before the reference voltage falls to 90% of its nominal value. Such low-supply-voltage and high-current-driving BGR in standard digital CMOS processes is highly useful in portable and switching applications.

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We report a novel analog delay circuit based on Miller effect that features small die area and tunable delay in the order of 100 mus, without using any external component. The delay time can be tuned by varying the biasing current, capacitor sizes, transconductance of the gain-stage transistor and the corresponding output impedances. The turn-on threshold of the delay circuit can also be raised, as required in some applications, by utilizing the body effect of the input transistors. The circuit has a very low startup voltage (ap0.9 V) and consumes a very low power (ap2.7 muW) in a standard 1 mum pure CMOS process with Vtn ap 0.65 V and Vtp ap 0.8 V at 25degC. Circuit operations are elaborated and its function is verified by simulation and silicon measurement.

W, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode

This paper presents an effective approach for designing switch mode power supply (SMPS) based on simple transfer functions. Empirical system loop gains for trailing-edge modulation voltage-mode and current-mode buck, boost, and buck-boost converters are listed and verified by laboratory measurement. The method allows practitioners to design DC-DC power converters in an efficient and systematic manner using Type-I, II, or III internal compensation circuitry. The contribution and trade-off of specific components to the system dynamics of a converter is easily captured in the proposed framework. An example demonstrating the optimized design of a stable boost converter is also elaborated.

A 0.9V 2.7µW small-area 100µs+ analog CMOS tunable-delay circuit utilizing Miller effect

In this paper, an Amplitude Shift Keying (ASK) demodulator circuit for Near Field Communication (NFC) target mode or Radio Frequency Identification (RFID) tag is designed by using sample and hold method. It features envelope detector, switch capacitor filter, dynamic comparator, clock extractor and phase generator. This demodulator was demonstrated and simulated in TSMC 0.18um CMOS technology with an average power of 32uW power consumption at 13.56Mbps Non-Return-to-Zero (NRZ) date rate for a carrier frequency of 13.56MHz. The minimum input voltage swing is 200mVpp.

An Efficient Transfer-Function-Based Approach for the Fast Tuning and Design of DC-DC Converters

A signal acquisition IC for 3-input resistive bridge sensors has been realized in 0.18um CMOS. It features a low noise programmable amplifier which achieved 1.8μVrms input referred noise and 120dB CMRR, a SAR ADC with 11.2 bits ENOB, an embedded temperature sensor and configurable oscillator. The active area of the chip is 0.3mm2 which consumes 60μW and 18μW at 1.8V supply with output data rate (ODR) of 400Hz and 100Hz respectively.

A 2.4pJ/bit ASK demodulator with 100% modulation rate for 13.56MHz NFC/RFID applications

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

A 0.3mm 2 60μW 11.2b ENOB signal acquisition ASIC for resistive bridge sensors

A re-configurable MASH ΣΔ ADC is implemented in 0.18μm CMOS process. The proposed technique configures the ADC architecture for optimal power for specific resolution and applications. For high performance applications, the first integrator stage of the cascaded modulator may be constructed from larger transistors and capacitors to reduce thermal and op amp noise. However, this larger first stage also consumes more power than later stages constructed from smaller transistors and capacitors. Thus the first stage tends to provide a higher resolution while consuming more power than later stages, which have lower performance and lower power consumption. The principal advantage of this architecture is that the ADC is adaptable for applications with different performance and power consumption requirements. Although the ADC was designed for audio applications, this re-configurability is also useful for multimode communication systems.

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

The growing markets of electronic components in automotive electronics, LCD/LED drivers and TV sets lead to an extensive demand of high-voltage integrated circuits (HVICs), which are normally built by HV-MOSFETs. These HV-MOSFET devices generally occupy large die areas and operate at low speed due to large parasitic capacitance and small transconductance (gm). There are two types of HV-MOSFET devices, namely, thick-gate and thingate oxide devices. Thick-gate oxide devices can sustain a high gate-to-source voltage, VGS, but suffer from a reduced gm, poor threshold voltage VT control in production and higher cost due to the need of extra processing steps. Thin-gate devices have a larger gm, smaller parasitic capacitance, less processing steps and a lower cost. These properties make the thingate HV-MOSFETs attractive, though they face severe limitation on VGS swing. There are two main concerns when thin-gate HV-MOSFETs are used. The first is how to achieve high current driving capability to drive capacitive loads in high-voltage (HV) application, whereas the second is how to protect the thin-gate oxide from HV stress breakdown. For current-driving capability, Bales (Bales, 1997) proposed a class-AB amplifier using bipolar technology which consumes a high quiescent current and is expensive due to a large die area and complicated masking. Lu & Lee (Lu & Lee, 2002) proposed a CMOS class-AB amplifier which can only drive around 6mA and does not meet the driver requirements of large and fast current responses (Hu & Jovanovic, 2008). Mentze et al. (Mentze et al., 2006) proposed a HV driver using pure low-voltage (LV) devices but this architecture requires an expensive silicon-on-insulator (SOI) process to sustain substrate breakdown in HV application. Tzeng & Chen (Tzeng & Chen, 2009) proposed a driver that consumes a large die area with all transistors inside the circuit being HV transistors. On the other hand, transistor reliability becomes a serious issue in HV thin-gate oxide transistor circuits. Chebli et al. (Chebli et al., 2007) proposed the floating gate protection technique. The voltage range under protection will change according to the ratio of capacitors and the HV supply, VDDH. This technique, however, cannot limit the voltage across the nodes of gate and source well when the variation of the supply voltage is large. Riccardo et al. (Riccardo et al., 2001) proposed a method which requires an extra Zener diode to protect the thin-gate oxide transistors, so a special process and higher cost are incurred. Declercq et al. (Declercq et al., 1993) suggested a HV-MOSFET op-amp driver with a clamping circuit to protect the thin-

A re-configurable 4 th order switched capacitor ΣΔADC for adjusting power and performance

We present a CMOS bandgap voltage reference with a low quiescent current and high output current driving capability of up to 1.5 mA. The circuit achieves a very low supply current of 11muA, a low power of 27 muW, a line regulation of plusmn2.5 mWV and a load regulation of 14mV/mA. The bandgap reference is implemented in a 1 mum pure CMOS process with Vthn ap |Vthp| ~0.9 V at 25degC. Experimental results show the silicon measurements are in good agreement with simulations. The proposed reference circuit constitutes a versatile solution in switching mode power supply (SMPS) and portable applications, due to its driving capability and low power consumption.