David Ludwig

3DANN-R : A tera-op convolution engine for image processing

A commercial version of the 3D Artificial Neural Network has been developed under a collaborative effort between JPL and Irvine Sensors, sponsored by BMDO and the U.S. Air Force. It is capable of continuous trillion eight bit multiply and add operations per second while consuming under ten watts. Its architecture, input-output characteristics, and performance data will be presented.

Optoelectronic interconnects for 3D wafer stacks

Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.