David M. Cohen

The AETG system: an approach to testing based on combinatorial design

This paper describes a new approach to testing that uses combinatorial designs to generate tests that cover the pairwise, triple, or n-way combinations of a systems test parameters. These are the parameters that determine the systems test scenarios. Examples are system configuration parameters, user inputs and other external events. We implemented this new method in the AETG system. The AETG system uses new combinatorial algorithms to generate test sets that cover all valid n-way parameter combinations. The size of an AETG test set grows logarithmically in the number of test parameters. This allows testers to define test models with dozens of parameters. The AETG system is used in a variety of applications for unit, system, and interoperability testing. It has generated both high-level test plans and detailed test cases. In several applications, it greatly reduced the cost of test plan development.

The combinatorial design approach to automatic test generation

The combinatorial design method substantially reduces testing costs. The authors describe an application in which the method reduced test plan development from one month to less than a week. In several experiments, the method demonstrated good code coverage and fault detection ability.

The Automatic Efficient Test Generator (AETG) system

Software testing is expensive, tedious and time consuming. Thus, the problem of making testing more efficient and mechanical, without losing its effectiveness, is very important. The Automatic Efficient Test Generator (AETG) is a new tool that mechanically generates efficient test sets from user defined test requirements. It is based on algorithms that use ideas from statistical experimental design theory to minimize the number of tests needed for a specific level of test coverage of the input test space. The savings due to AETG are substantial when compared to exhaustive testing or other methods of testing. AETG has been used in Bellcore for screen testing, interoperability testing and for protocol conformance testing. The paper describes the current system and it constructs and reports some preliminary results obtained during initial trials.<<ETX>>

The IC* model of parallel computation and programming environment

The IC* project is an effort to create an environment for the design, specification, and development of complex systems such as communication protocols, parallel machines, and distributed systems. The basis of the project is the IC* model of parallel computation, in which a system is specified by a set of invariant expressions which describe its behavior in time. The features of this model include temporal and structural constraints, inherent parallelism, explicit modeling of time, nondeterministic evolution, and dynamic activation. The project also includes the construction of a parallel computer specifically designed to support the model of computation. The authors discuss the IC* model and the current user language, and describe the architecture and hardware of the prototype supercomputer built to execute IC* programs. >

The IC system for protocol development

The realization of a new protocol is a long and complicated procedure whose inherent technical difficulty is exacerbated by the scarcity of useful tools. This paper discusses the initial use of a system that is being developed by Bell Communication Research to help in the specification, analysis, and implementation of communications protocols. This paper describes the application of this system to the specification and implementation of an industry standard protocol.

Rapid prototyping of communications protocols using a new parallel language

A description is given of the L.0 language, a parallel, high-level executable specification language created for the design and implementation of software systems with inherent concurrency, such as communications protocols, services and networks. L.0 was explicitly designed to express coordination, simultaneity, and the hierarchical composition of systems from component subsystems. L.0 has been used to prototype communications protocols and services and to study network architectures and switching systems. The application of L.0 to the prototyping of a large portion of an experimental data communication services network architecture is discussed.<<ETX>>

Weighted Binary Trees for Concurrent Searching

A traditional cost measure for binary search trees is given by weighted path length, which measures the expected cost of a single random search. In this paper, we investigate a generalization, thek-cost, which is suitable for applications involving independent parallel processors each utilizing a common search tree. Thek-costis defined to be the expected value of the maximum length of the search paths encountered during the course ofkindependently performed random searches. For example, ifk=1, then thek-costrepresents the traditional weighted path length. Our results include efficient algorithms for constructing binary search trees having near optimalk-cost. An interesting feature of one of our algorithms concerns the fact that it constructs a search tree that simultaneously has near optimalk-costfor allk; in fact, the structure of this tree is determined only by the order permutation of the sequence of probability weights that are to be assigned to the tree nodes. This stands in contrast to an example which shows that a tree which is precisely optimal relative to weighted path length (1-cost) can havek-costwhich is exponentially greater than thek-costof the optimal tree. We also investigate connections between splaying andk-cost. In pursuing this connection we define a problem, thecurator problem, which is approximately dual to the problem of optimalk-cost, and then use this duality to elucidate certain aspects of the dynamic optimality conjecture for splay trees.

Products of finite state machines with full coverage

Given a collection of finite state machines, {M i }, with the same input alphabet, let M be the product machine, M=πM j . In general, not every state in M is reachable. A natural question is whether there are any inherent limits to the number of reachable states in a system that is the product of many small finite state machines. This note constructs a family of product machines M where the number of states is doubly exponential in the number of states in any individual machine M i and every product state is reachable.

The IC model of parallel computation and programming environment

The IC* project is an effort to create an environment for the design, specification and development of complex systems such as communication protocols, parallel machines and distributed systems. The basis of this work is the IC* model of parallel computation. In this model a system is specified by a set of invariant expressions which describe its behavior in time. The novel features of the model include: temporal and structural constraints, inherent parallelism, explicit modeling of time, nondeterministic evolution and dynamic activation. The project also includes the construction of a parallel computer specifically designed to support the model of computation. The model of computation, the status of the project and the user environment is the content of this paper.

IC* Supercomputing Environment

The IC* project is an effort to create an environment for the design, specification, and development of complex systems. Examples of such complex systems are communications and real time software and protocols, hardware, and physical and econometric models.