David O. Erstad

Radiation-hard circuit

L-and U-gate devices for SOI/SOS applications

Dual redundant dynamic logic

Glitch removal circuitry

Digital Single Event Transient Hardened Register Using Adaptive Hold

Circuit architecture for radiation resilience

System and method for obtaining hysteresis through body substrate control

Single event hardening of null convention logic circuits

Voting scheme for analog signals

System level hardening of asynchronous combinational logic