David R. Ditzel

Register allocation for free: The C machine stack cache

The Bell Labs C Machine project is investigating computer architectures to support the C programming language.1 One of the goals is to match an efficient architecture to the language and the compiler technology available. Measurements of different C programs show that roughly one out of every twenty instructions executed is either a procedure call or return.2 Procedure call overhead is therefore a very important consideration in the overall machine design. A second and related area of primary concern in overall machine efficiency is the register allocation strategy. While use of additional registers can offer considerable improvement in execution times, adding registers usually has the adverse effects of increasing the procedure call overhead due to register saving and creating an undue burden on the compiler. In this paper we describe a piece of the C Machine architecture which effectively eliminates the register allocation problem, and improves procedure calling by drastically reducing storage references required by traditional register saving. The technique can be generalized for other languages and architectures, though we will only directly address those issues involving the C language.

Branch folding in the CRISP microprocessor: reducing branch delay to zero

A new method of implementing branch instructions is presented. This technique has been implemented in the CRISP Microprocessor. With a combination of hardware and software techniques the execution time cost for many branches can be effectively reduced to zero. Branches are folded into other instructions, making their execution as separate instructions unnecessary. Branch Folding can reduce the apparent number of instructions needed to execute a program by the number of branches in that program, as well as reducing or eliminating pipeline breakage. Statistics are presented demonstrating the effectiveness of Branch Folding and associated techniques used in the CRISP Microprocessor.

The hardware architecture of the CRISP microprocessor

The AT&T CRISP Microprocessor is a high performance general purpose 32-bit processor. It has been implemented as a single CMOS chip containing 172,163 transistors in a 1.75~t CMOS technology and runs at a clock frequency of 16 MHz. 1 The CRISP Microprocessor achieves performance through traditional techniques, such as pipelining, and from several new techniques not before found in microprocessor designs. This paper focuses on a detailed description of hardware architecture, including the pipeline structure and details of the architectural innovations. A brief introduction to the instruction-set and major features are given for background.

Retrospective on high-level language computer architecture

High-level language computers (HLLC) have attracted interest in the architectural and programming community during the last 15 years; proposals have been made for machines directed towards the execution of various languages such as ALGOL, 1,2 APL, 3,4,5 BASIC, 6,7 COBOL, 8,9 FORTRAN, 10,ll LISP, 12,13 PASCAL, 14 PL/I, 15,16,17 SNOBOL, 18,19 and a host of specialized languages. Though numerous designs have been proposed, only a handful of high-level language computers have actually been implemented. 4,7,9,20,21 In examining the goals and successes of high-level language computers, the authors have found that most designs suffer from fundamental problems stemming from a misunderstanding of the issues involved in the design, use, and implementation of cost-effective computer systems. It is the intent of this paper to identify and discuss several issues applicable to high-level language computer architecture, to provide a more concrete definition of high-level language computers, and to suggest a direction for high-level language computer architectures of the future.

Using CAD Tools in the Design of CRISP

CRISP is a high-performance 32-bit RISC microprocessor that uses 172,163 transistors in a 1.75¿m CMOS technology. The large chip size of 10.35 mmx 12.23 mm and complexity of the design required an extensive top-down approach in a set of integrated design tools. CAD tools ranged from an instruction set interpreter to detailed timing simulation. Practical problems encountered include communication among different tools and limits on process size, file size, and total compute time. Use of both symbolic compaction and physical layout, while improving initial efficiency, created problems later in the design.

Reflections on the High-Level Language Symbol Computer System

A radical computer architecture implementing a programming language and a timeshared operating system directly in hardware, Symbol remains a valuable lesson in building complex systems.

Retrospective: a retrospective on high-level language computer architecture

vv ritten at the end of 1979, this paper challenged the 1970’s trend in computer architecture toward ever increasing complexity. The decade of the 1970’s was dominated by the growing influence of micro-coded minicomputers such as the Digital Equipment Corporation VAX computers. The VAX had over 200 instructions with complex addressing modes. Micro-coded implementations of computer instruction sets meant that adding new instructions was relatively easy. Research in computer architecture during the 1970’s often proposed far more complicated computer hardware that would move towards implementing high level languages directly in hardware in order to facilitate programming in high level languages. Recall that during the 1970’s there still existed considerable debate as to whether programming in high level languages would be too inefficient in both performance and code space. This paper reflected a mood that something was wrong with the direction of computer architecture research. The paper started by repeating six commonly held beliefs (“Axioms”) of the day that we felt were not well justified, and ended with an appeal that what mattered was the effect of the combined hardware/software system, and not which individual component was implemented in hardware. In many ways, this retrospective set our direction toward the RISC movement of the 1980’s, and heavily influenced us in our research and further publication on RISC processors. Our first paper on RISC was published only five months after this first retrospective paper appeared. Re-reading this paper 18 years later, we are surprised by how well it holds up. Most surprisingly, many of the same issues about High-level Language Computers are again resurfacing with proposals to implement JAVA byte-codes directly in hardware. Stack machines, byte-coded instruc-

Experience with CAD Tools for a 32-Bit VLSI Microprocessor

As the complexity of VLSI devices increases, so does the need to rely on computer aided design (CAD) methods. As VLSI designs grow they push the limits of the CAD tools, and in some cases require new approaches to design and verification. This paper reports on experiences with a particular approach taken to design a 170,000 transistor single chip CMOS microprocessor. The chip was an implementation of the Bell Labs C-Machine 1, 2 architecture, code-named CRISP (C-Machine Reduced Instruction Set Processor) during its design. The major design tools used are described along with pleasant and unpleasant surprises in their use. Problems with more traditional approaches due to the increased size of designs are discussed.