David R. Martinez

Field programmable gate array based radar front-end digital signal processing

As Field programmable Gate Array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPCA technology. As this paper demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 5 MHz (with a clock rate of at least 40 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation. Distributed arithmetic was determined to be the most optimal structure for a FPGA FIR design, although future research may show that fast FIR algorithms or filtering in the frequency domain might give better results.

Application of parallel processors to real-time sensor array processing

Historically, most radar sensor array processing has been implemented using dedicated and specialized processing systems. This approach was necessary because the algorithm computation requirements were several orders of magnitude higher than any commercial supercomputer could provide in an acceptable size, weight and power. Most recently, with the interest by the military to employ commercial-off-the-shelf (COTS) technology, and the rapid advances in computation throughput by COTS supercomputers, we are able to meet the present algorithm requirements with COTS massively parallel processors (MPPs). However, there are still many issues to be overcome to get the most out of a parallel processor for our application. Some of the important issues are the balance between high computation throughput and total exchange communication over the processor network, message passing or shared memory access with high communication throughput for small message sizes, and the scalability of these machines to more demanding algorithm and application requirements. In this paper we present the application requirements, review the important computational kernels, and conclude with our experiences in evaluating representative MPPs.

Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor

Many radar sensor systems demand high performance front-end signal processing. The high processing throughput is driven by the fast analog-to-digital conversion sampling rate, the large number of sensor channels, and stringent requirements on the filter design leading to a large number of filter taps. The computational demands range from tens to hundreds of billion operations per second (GOPS). Fortunately, this processing is very regular, highly parallel, and well suited to VLSI hardware. We recently fielded a system consisting of 100 GOPS designed using custom VLSI chips. The system can adapt to different filter coefficients as a function of changes in the transmitted radar pulse. Although the computation is performed on custom VLSI chips, there are important reasons to attempt to solve this problem using adaptive computing devices. As feature size shrinks and field programmable gate arrays become more capable, the same filtering operation will be feasible using reconfigurable electronics. In this paper we describe the hardware architecture of this high performance radar signal processor, technology trends in reconfigurable computing, and present an alternate implementation using emerging reconfigurable technologies. We investigate the suitability of a Xilinx Virtex chip (XCV1000) to this application. Results of simulating and implementing the application on the Xilinx chip is also discussed.

ISR sensor processing and data exploitation

Intelligence, Surveillance, and Reconnaissance, commonly abbreviated as ISR, refers to the system of sensors (data collection assets) and data analysis and dissemination resources used to provide information about strategic and tactical threats. The advances in ISR sensor technologies and the large amount of data generated from ISR systems are putting a significant demand on signal processing and data exploitation. For example, an electro-optical system can easily generate several billion bits per second while searching an area the size of a small city. Therefore, onboard front-end signal processing is needed to reduce the amount of information to a manageable size and to make the outputs compatible with existing and future communication links. Similarly, there is increasing interest in allowing data exploitation on board the platforms. This talk will address examples of front-end signal processing, demands in data exploitation, and associated high-performance embedded computing for ISR systems. The discussion will conclude with an emphasis on graph exploitation approaches to address the conversion of sensor information into knowledge that military forces and/or strategic analysts can act on in a timely manner.

Future Challenges In The Development Of Real-time High Performance Embedded Systems

In designing the portable embedded system, power consumption would be an important issue. Numerous prior issues of power dissipation have been discussed, and there are fewer functions (such as power measurement, power analysis, and power management) supporting for a SoC embedded system development learning board. In order to help designer to get power information in the beginning of design, we propose a development platform for power analysis and build an analysis system for power analysis. The system describes in this paper that has three important features power measurement, power analysis, and power management. By using this system, it can help us to design the development of high performance embedded system designs with low power consumption. This system has been implemented on the real embedded systems to demonstrate the functionalities which we proposed.

Architecture for Machine Learning Techniques to Enable Augmented Cognition in the Context of Decision Support Systems

For a wide range of applications, one of the key challenges is to identify an architecture that is suitable for machine learning techniques to enable important augmented cognition capabilities in the context of complex decision support systems. This overview paper presents an architecture framework. The elements of the architecture are described starting with data formatting, a machine learning algorithm taxonomy, components of courses of action, resource management, and finally the role of augmented cognition within the architecture. The paper includes one cyber security example where the architecture framework is employed. The paper concludes with future work in the development of a recommender system.

Embedded Digital Signal Processing for Radar Applications

In the last ten years, there has been significant emphasis on advancing sensor systems with active electronically scanned antennas (AESAs). The recent advances in computing technologies make it affordable to exploit the flexibility of AESAs using very high performance embedded computers for signal and image processing. This tutorial presents an overview of applications demanding real-time embedded computing, an introduction to hardware and software implementation techniques, recent advances in hardware and software standards to achieve rapid technology insertion, and a look into observed embedded computing trends.