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Featured researches published by David R. Stauffer.


Ibm Journal of Research and Development | 1996

Design methodology for IBM ASIC products

James J. Engel; Thomas S. Guzowski; Anderson Herrick Hunt; David E. Lackey; Lansing D. Pickup; Robert A. Proctor; Karla Reynolds; Ann Marie Rincon; David R. Stauffer

The IBM ASIC design methodology enables a product developer to fully incorporate the high-density, high-performance capabilities of the IBM CMOS technologies in the design of leading-edge products. The methodology allows the full exploitation of technology density, performance, and high testability in an ASIC design environment. The IBM ASIC design methodology builds upon years of experience within IBM in developing design flows that optimize performance, testability, chip density, and time to market for internal products. It has also been achieved by using industry-standard design tools and system design approaches, allowing IBM ASIC products to be marketed externally as well as to IBM internal product developers. This paper describes the IBM ASIC design methodology, and then focuses on the key areas of the methodology that enable a customer to exploit the technology in terms of performance, density, and testability, all in a fast-time-to-market ASIC paradigm. Also emphasized are aspects of the methodo logy that allow IBM to market its design experience and intellectual property.


Archive | 2003

System and method for optimizing iterative circuit for cyclic redundancy check (CRC) calculation

Ming-I M. Lin; David R. Stauffer


Archive | 1997

Test mode matrix circuit for an embedded microprocessor core

Cory Ansel Cherichetti; Peter Stewart Colyer; David R. Stauffer


Archive | 2004

Method, system and program product for building an automated datapath system generating tool

David R. Stauffer; Jeanne Trinko-Mechler


Archive | 1992

FDDI network test adaptor error injection circuit

Thomas Eckenrode; David R. Stauffer; Rebecca Stempski


Archive | 1995

Direct memory access acceleration device for use in a data processing system

David R. Stauffer; Rebecca Stempski Mcmahon


Archive | 2003

SYSTEM AND METHOD FOR DATA PHASE REALIGNMENT

Sheehan D. Lake; David R. Stauffer


Archive | 2004

Iterative circuit and method for variable width parallel cyclic redundancy check (crc) calculation

Ming-I M. Lin; David R. Stauffer


Archive | 2003

HIGH SPEED CLOCK DIVIDER WITH SYNCHRONOUS PHASE START-UP OVER PHYSICALLY DISTRIBUTED SPACE

Douglas C. Pricer; David R. Stauffer


Archive | 2008

Automated simulation testbench generation for serializer/deserializer datapath systems

Francis A. Kampf; Jeanne Trinko-Mechler; David R. Stauffer

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