David Y. Feinstein

Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits

This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.

Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities

System security continues to be of increasing importance. To effectively address both natural and intentional threats to large systems, the threats must be cataloged and analyzed. Extremely large and complex systems can have an accordingly large number of threat scenarios. Simply listing the threats and devising countermeasures for each is ineffective and not efficient. We describe a threat cataloging methodology whereby a large number of threats can be efficiently cataloged and analyzed for common features. This allows countermeasures to be formulated that address a large number of threats that share common features. The methodology utilizes Multiple-Valued Logic for describing the state of a large system and a multiple-valued decision diagram (MDD) for the threat catalog and analysis.

System-on-Chip Power Consumption Refinement and Analysis

Accurate power consumption estimation of a System-on-Chip (SoC) using modeling techniques is difficult due to the diverse mixture of processes with radically different current consumption. It is very important that these estimations will be fine tuned to the specific SoC with accurate current measurement during the design and prototyping phase. We introduce an accurate method to measure power consumption using a single measurement point and a dynamic logging algorithm. We present a demonstration tool for continuous logging of the instantaneous power consumption with an identification of the running process within the SoC. Our approach can also be used to steer the dynamic power management (DPM) of a SoC.

On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams

This paper describes new metrics for the data structure referred to as quantum multiple-valued decision diagrams (QMDD) which are used to represent the matrices describing reversible and quantum gates and circuits. These metrics provide information about QMDD that allows for improvement of minimization techniques. We explore metrics related to the frequency of edges with non-zero weight for the entire QMDD data structure and their histograms with respect to each variable. We observe some unique regularity particular to the methodology of the QMDD. We develop new heuristics for QMDD dynamic variable ordering (DVO) that are guided by the proposed metrics. Experimental results show the effectiveness of the proposed techniques.

Variable Reordering and Sifting for QMDD

This paper considers variable reordering for quantum multiple-valued decision diagrams (QMDD) used to represent the matrices describing reversible and quantum gates and circuits. An efficient method for adjacent variable interchange is presented and this method is employed to implement sifting of QMDDs. Experimental results are presented showing the effectiveness of the proposed techniques.

On the Skipped Variables of Quantum Multiple-Valued Decision Diagrams

The data structure referred to as quantum multiple-valued decision diagrams (QMDD) is used to efficiently represent the unitary matrices describing reversible and quantum circuits. This paper investigates the conditions that cause skipped variables to appear in the QMDD of some binary and ternary quantum circuits. We have found that a unitary matrix that produces a skipped variable in a QMDD is likely to cause a specific anomaly when it is decomposed into a cascade of two-level unitary matrices by the Beck-Zeilinger-Bernstein-Bertani algorithm.

Advances in Quantum Computing Fault Tolerance and Testing

We study developments in quantum computing (QC) testing and fault tolerance (FT) techniques and discuss several attempts to formalize quantum logic fault models. We illustrate the inherent need for fault tolerance in QC due to the decoherence problem. Further, we examine several ideas regarding random testing and examine the viability of built-in-system-test (BIST) in future QC circuits.

On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering

This paper proposes a framework that improves reversible logic synthesis by employing a dynamically determined variable order for quantum multiple-valued decision diagrams (QMDD). We demonstrate our approach through augmentation of the Miller-Maslov-Dueck (MMD) algorithm that processes the complete function specification in lexicographical order with our technique. We represent and minimize the complete specification with the QMDD and then synthesize the function specification based on the minimized variable order. The framework produces significantly smaller reversible circuits in many cases. Experimental results also show the effectiveness of using the QMDD size as a measure of the complexity of MVL and binary reversible circuits.

Prefix Parallel Adder Virtual Implementation in Reversible Logic

This paper demonstrates a simplified approach for reversible logic synthesis based on direct translation of the circuit VHDL description into virtual Fredkin gates. We investigate the size and speed of such a reversible logic implementation of the Brent-Kung Parallel Prefix Adder (PPA) in comparison to a standard logic implementation. Using the Altera Corporations Quartic II synthesis and simulation tool, we show that our virtual reversible logic implementation follows the O(log2n) delay and O(n) cost of the standard logic implementation.

Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation

We present a brief survey of recent developments in reversible sequential circuits and quantum finite state machines based on both binary and multiple-valued solutions. We then argue the benefits of adapting the asynchronous approach for reversible sequential circuit design. We offer several new reversible implementations of key elements to be used in reversible asynchronous pipelines. We investigate the physical reversibility of the proposed design.