Dean Nobunaga
Micron Technology
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Publication
Featured researches published by Dean Nobunaga.
international solid-state circuits conference | 2008
Dean Nobunaga; Ebrahim Abedifard; Frankie F. Roohparvar; June Lee; Erwin Yu; Allahyar Vahidimowlavi; Michael M. Abraham; Sanjay Talreja; Rajesh Sundaram; Rod Rozman; Luyen Vu; Chih Liang Chen; Uday Chandrasekhar; Rupinder Bains; Vimon Viajedor; William Mak; Munseork Choi; Darshak Udeshi; Michelle Luo; Shahid Qureshi; Jeffrey Tsai; Frederick Jaffin; Yujiang Liu; Marco Mancinelli
A 3.3V 8Gb NAND flash memory with a synchronous double-data-rate (DDR) interface is designed and fabricated using 3M 50nm technology to meet the requirements of the markets. This paper achieves a NAND flash program throughput of 100 MB/s with quad-plane operation, which is 5x previously reported. I/O read/write throughput of 200MB/s is achieved using a newly developed DDR interface and data path. The chip features a dual interface, supporting both the newly developed synchronous DDR interface as well as the standard, asynchronous NAND flash interface.
Archive | 2010
Dean Nobunaga; Hanqing Li
Archive | 2001
Frankie F. Roohparvar; Dean Nobunaga
Archive | 2000
Frankie F. Roohparvar; Dean Nobunaga
Archive | 2000
Dean Nobunaga; Frankie F. Roohparvar
Archive | 2011
Dean Nobunaga; June Lee; Chih Liang Chen
Archive | 2008
Dean Nobunaga
Archive | 2000
Dean Nobunaga; Frankie F. Roohparvar
Archive | 2006
Dean Nobunaga
Archive | 2009
Dean Nobunaga
