Denis Deschacht

Illustration of the importance of on-chip self and mutual inductances

Transmission line properties of on-chip wiring need to be taken into account due to the great lengths and fast rise times encountered. In this paper, we show the influence of on-chip self and mutual inductances on timing performances by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and on the other with the drivers in opposite directions. The differences observed, when the currents in the lines flow in the same direction as opposed to the cases when the currents are in opposite directions shows clearly the influence of mutual inductance. A second comparison ignoring inductive effects shows a discrepancy rate reaching as high as 50% for the output switching delay.

Theoretical limits for signal reflections due to inductance for on-chip interconnections

Transmission line properties of on-chip wiring need to be taken into account due to the great lengths and fast rise times encountered. As the line lengths and circuit speeds increase, the wavelength decreases, and the distributed n-section RC representation will be no longer adequate to analyse signal integrity. With these trends it is becoming more important to include inductance when modeling on-chip interconnect. The electrical phenomena that have to be investigated are governed by the electromagnetic theory. We present first in this paper an efficient and accurate modeling and simulation technique of frequency-dependent transmission lines to determine interconnection characteristics. The electromagnetic approach is then used to determine the limits where effects such as signal reflections can be predicted. The theoretical limits calculated are then illustrated.

Proximity Effect of Neighbour Victim Lossy Interconnects on a Single Attacker and Vice Versa

Signal integrity on a set from three to eight lossy copper interconnects of less than one square micron is determined from a transient simulation based on electrical circuit representation. This circuit is deduced from a full wave finite element method. Our signal integrity results on numerous possible excitations show that two neighbour interconnects on both sides of a reference aggressor or victim is sufficient to predict more complex situation on largest number of wires. This means that the five interconnects case is also well appropriate. We have verified that it is the best compromise whatever the permittivity of dielectric material which filled the spacing between interconnects, as well as the width of this spacing.

On-chip interconnections: impact of adjacent lines on timing

As the CMOS technology scales down, the coupling capacitance between adjacent wires plays dominant part in wire load and interference becomes a serious problem for VLSI design. In this paper, we focus on delay increase caused by adjacent lines. This increase in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. We propose an analytical expression to compute the delay in the presence of coupling that takes explicitly into account interconnect resistance and capacitance, driver resistance and relative driver strengths.

Crosstalk pulsewidth calculation

A new RLC crosstalk noise expression, based on an RLC transmission line model propagating each propagation mode, has recently been proposed and has been validated in previous works. From this expression, we propose in this paper to calculate the noise characteristics such as the maximum amplitude and the noise pulsewidth. Generally, it is better to use closed form expressions instead of simulation tools to predict coupling effects in a circuit and evaluate noise voltages characteristics. They provide information on the way to modify the circuit structures or interconnect designs in order to reduce or control crosstalk noise more rapidly than by setting about electrical simulations.

DSM interconnects: importance of inductance effects and corresponding range of length

To analyze at which rise/fall times the inductance effect appears in DSM interconnects, the author develops a methodology versus the input line transition time to be technology-independent. These lines are modeled as RC and RLC distributed lines, and the two models are compared to define the effects caused by neglecting inductance. The goal of this study is, based upon the discrepancy between RC and RLC models, to define when inductance must be included in the modeling of interconnects. A simple rule permits the choice of the simplest model (RC or RLC) for a given accuracy. The length range concerned by the inductive effect is calculated from the complex propagation factor value. The theoretical limits are illustrated on several interconnection configurations, on a 0.18-mum technology

Performances of coupled interconnect lines: the impact of inductance and routing orientation

In this paper we show the influence of inductance and routing orientation on timing performances by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and the other with the drivers in opposite directions. For a typical DSM (deep-sub-micron) process, we show that when analyzing VLSI circuits, if standard distributed RC models are used, and inductive effects and routing orientation are ignored, large errors can occur in the prediction and evaluation of the circuit behavior. Both greatly affect circuit performances: the discrepancy rates can reach 20% and 18% respectively for the latency and 50% and 30% for the output switching delay. The routing orientation can lead to a difference of 18% for the latency and 35% for the output transition time when the two lines have the same transitions.

Impact of inductance on timing characteristics of VLSI interconnects

As the result of the scaling down of technology and increased chip sizes, the cross-sectional area of wires has been reduced. With these trends, it is becoming crucial to be able to determine which nets within a high speed VLSI circuit exhibit prominent inductive effects. The object of this paper is to answer a question frequently put to designers: is inductance necessary to model interconnections or can a simple RC model be sufficient? By comparing the simulation results obtained from electrical simulations to an electromagnetic approach we can verify if the RC distributed model is always sufficient to characterize the propagation delay and the degradation due to the interconnect lines in submicronic circuit. Limits between RC and RLC models are determined.

Interconnect design for a 32 nm node technology

When high speed integrated circuits technology scales down from one node to the other, ITRS suggests a reduction in sizes by a factor of around square of 2, and recommends 17% of improvement on performance. But the obtained gain on active devices is foiled by an increase of interconnect propagation delays and critical crosstalk levels in the Back End of Line (BEOL). This issue especially concerns interconnect of the intermediate metal level. Our works are focused on the impact on signal transmission delay along interconnects of decreasing the space and width. To avoid new industrial manufacturing constraints on cost and reliability, this study is performed without modifying process and materials used in the BEOL of CMOS 45 nm IC. We will study interconnects of 50 nm width, with a 50 nm space between lines in accordance with speed and crosstalk levels requirements of CMOS 32 nm BEOL. When it becomes hard to meet all requirements, it is shown that interconnect density constraints should be relaxed to enlarge the scope of application.

Parasitic influence, on signal integrity, of several victim lines placed asymmetrically beside and symmetrically at both sides of an attacker interconnect and mutually

Far end crosstalk on victim lines located near an aggressor as well as rise time and propagation delay at the end of the attacker are evaluated. It is done thanks to a home made software based on full wave electromagnetic finite element and transient analysis simulation. These investigations are carried out when the aggressor lossy interconnect of less than one micron square area is symmetrically and asymmetrically placed in an arrangement of three, five and eight copper lossy lines, in case of low, medium and strong mutual effects. Our signal integrity points out that two neighbour lines on both sides of an active interconnect (i.e. the aggressor) are a good compromise to understand more complicated situation on greatest number of unintentionally coupled interconnects. We have verified this fact even in case of small spacing or high permittivity material which filled partially the spacing between interconnects (i.e. strong mutual effects).