Dennis Heinrich

Accelerated join evaluation in Semantic Web databases by using FPGAs

While the amount of information steadily increases, the requirements on the response time to query these information become more strict. Under those conditions, conventional database systems reach their limits and cannot meet these performance requirements anymore. In recent years, systems with many processing cores are considered to satisfy these demands. Furthermore, these systems include more and more heterogeneous cores tailor‐made to solve one specific task in an efficient manner. However, dedicated hardware accelerators are inflexible and cannot be adapted to the requirements of a dedicated query. Thus, the challenge is orchestrating the diversity of the functionality of all the cores to be optimized for performance/energy efficiency. In this paper, a concept is introduced on how to develop a flexible Field‐Programmable Gate Arrays (FPGA)‐based hardware accelerator to improve the performance of query evaluation in a Semantic Web database. As a first step to the hardware/software system, several joint algorithms are implemented on an FPGA and evaluated against a well‐developed software solution (implemented in C). The comparison shows a significant speedup of up to 10 times. Because of the complexity of the join operator, it is promising that the overall performance of query evaluation can be further enhanced by processing whole queries on an FPGA. Copyright

Automated composition and execution of hardware-accelerated operator graphs

In this paper, we present the fully automated composition and execution of Semantic Web queries within a hardware/software system which uses a Field Programmable Gate Array (FPGA) as an accelerator. The presented approach allows to write a query in the databases front-end, transparently executes all steps to retrieve a configuration suitable for the FPGA which represents the given query, and obtains the result by evaluating the query on the FPGA. In order to obtain a runtime-reconfigurable framework we define a static and a dynamic partition. The dynamic partition itself is composed by using a predefined query template and a pool of operators. The operators of the given query are written automatically into the template and connected accordingly. After reconfiguration of the FPGA the host system supplies the initial data to the FPGA which computes the final result and sends it back to the host system to be displayed to the user or application. The evaluation shows that not all queries may take benefit from a dedicated hardware-accelerator but shows promising speedup for complex queries.

Hybrid FPGA approach for a B + tree in a Semantic Web database system

In this paper we present a hybrid index structure which is allocated in a Field Programmable Gate Array (FPGA) and a traditional CPU-based host system. The used index structure of this system is a B+-tree which is a common index used in disk based databases. The hybrid index is divided into two parts. The lower levels of the B+-tree, especially the leaves where the values are stored, are located on the host system while the root and the most upper levels with the interior nodes are stored on the FPGA. We speed up the search in the upper levels of our hybrid index by applying an FPGA accelerated parallel search. In the evaluation we show how the amount of keys inside the interior nodes on the FPGA and the order of the B+-tree take an impact on the whole hybrid system. The results show that the computation time of the software system can be halved.

Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases

In this paper, we investigate the use of Field Programmable Gate Arrays (FPGAs) to enhance the performance of filter expressions in Semantic Web databases. The filter operator is a central part of query evaluation. Its main objective is to reduce the amount of data as early as possible in order to reduce the calculation costs for succeeding and more complex operators such as join operators. Due to the proximity to the data source it is essential for the overall query performance that the filter operator is able to evaluate single data items as fast as possible. In this work, the advantages of using FPGAs in query evaluation are outlined and an overview about the provided degree of parallelism is given. We propose two different approaches to implement the filter operator for the Semantic Web database LUPOSDATE. The Fully-Parallel Filter evaluates all conditions by dividing the input into several sub-items which are evaluated by dedicated sub-filters in parallel. The second approach creates a pipeline of sub-filters to evaluate the filter expression step-by-step. If an item reaches the end of this pipeline then it complies the whole filter expression. The final evaluation shows that both approaches of the hardware-implemented filter operator defeat the comparable software solution written in C running at 2.66 GHz. Processing 100M items per second, the hardware-accelerated filter running at 200 MHz provides a more than 5 times higher throughput than the general-purpose CPU. In contrast to the software solution, the total throughput is independent of the match rate and the structure of the filter expression, and is a valuable contribution to the hardware-accelerated query evaluation.

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases

In this paper, a data structure and a hardware acceleration for dictionary generation for Semantic Web databases are presented. Current hardware accelerators for databases are based on co-processor designs supporting software-centric applications: only single, selected operations of query processing are offloaded to the FPGA with time-consuming data transfers. In contrast, we propose a novel FPGA-centric design, which creates and manages specialized database structures. As part of the design, a scalable and parallel architecture for dictionary generation is introduced. We propose optimizations for Radix- Trees, which are designed to exploit characteristics of FPGA structures. Furthermore, the tree is parameterizable which enables the adaptation of properties to the specific characteristics of the generated data structure. The configuration influences memory and logic utilization. Optimal parameters are determined by simulative evaluation using existing Semantic Web input data sets. The proposed hardware design is integrated into an existing Semantic Web database system and the results are analyzed with a focus on utilization and throughput. The required memory of the optimized Radix-Tree is reduced by 94% and a speed-up of 70% is achieved.

Search & Update Optimization of a B\(^+\) Tree in a Hardware Aided Semantic Web Database System

This paper presents a hybrid architecture for accelerating search and update operations on Semantic Web indices. This database system uses a B\(^+\)-tree index structure distributed in a Field Programmable Gate Array (FPGA) and a CPU-based host system. The index is divided into two parts. The host system stores the values and the keys of the lower levels of the B\(^+\)-tree while a certain amount of the frequently accessed levels including the tree root is stored in the FPGAs internal and attached memory. Inside the FPGA we accelerate search operations by exploiting the parallel nature of the FPGA. By this, update operations can benefit from the speed up of their necessary searches. Furthermore, we estimate the performance based on the given experiments in a worst case scenario.

Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications

In this paper, a scalable hardware architecture for string sorting in the application field of Big Data is presented. Current hardware architectures focus on the acceleration of sorting small sets of data with a maximum string length. In contrast, we propose an FPGA-accelerated architecture based on Radix-Trees, which has the ability to sort large sets of strings without practical limitation of the string length. The Radix-Tree is parameterizable and so is the design, which enables the adaptation for application-specific properties, such as diversity of strings and size of the used alphabet. The scalable design has a hierarchical processing and memory architecture, which operate in parallel. Optimal parameters and configurations are evaluated by using a dataset of the Semantic Web, as an example of Big Data applications. The results are analyzed with a focus on throughput, memory requirement, and utilization. The hardware design is faster for all values of the radix parameter and achieves a maximum speed-up factor of 2.78 compared to a software system.

Hardware-aided update acceleration in a hybrid Semantic Web database system

In this paper, we focus on update optimizations in a Semantic Web database system aided by a field programmable gate array (FPGA). Many databases utilize B

Distributed Join Approaches for W3C-Conform SPARQL Endpoints

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