Desmond A. Kirkpatrick

Repeater scaling and its impact on CAD

We study scaling in the context of typical block-level wiring distributions, and identify its impact on the design process. In particular, we study the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for physical synthesis and full-chip assembly, showing that mere capacity scaling of current algorithms and methodologies is insufficient to handle the new challenges. Finally, we suggest a few approaches to tackle these challenges by constructing a case for abstract fabrics.

Miller factor for gate-level coupling delay calculation

In coupling delay computation, a Miller factor of more than 2/spl times/ may be necessary to account for active coupling capacitance when modeling the delay of deep submicron circuitry in the presence of active coupling capacitance. We propose an efficient method to estimate this factor such that the delay response of a decoupling circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and 0.5V/sub DD/ as the switching threshold voltage, an upper bound of 3/spl times/ for maximum delay and a lower bound of -1/spl times/ for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computing the Miller factor or effective capacitance. This result is highly applicable to crosstalk coupling delay calculation in deep submicron gate-level static timing analysis. Detailed analysis and approximation are presented. SPICE simulations are demonstrated to show high correlation with these approximations.

The scaling challenge: can correct-by-construction design help?

We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. In particular, we look at the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for logic synthesis, technology mapping, layout, and full-chip assembly, and identify several new research problems relevant to future designs. Next, we introduce the basic principles of correct-by-construction (CbC) design. We look at some techniques for post-RTL design meeting CbC philosophy, and then construct a case for flexible, abstract fabrics. Finally, we suggest CbC approaches to tackle the new synthesis and layout challenges identified in this paper.

Switching window computation for static timing analysis in presence of crosstalk noise

Crosstalk effect is crucial for timing analysis in very deep submicron design. In this paper, we present and compare multiple scheduling algorithms to compute switching windows for static timing analysis in presence of crosstalk noise. We also introduce an efficient technique to evaluate the worst case alignment of multiple aggressors.

EDA challenges facing future microprocessor design

As microprocessor design progresses from tens of millions of transistors on a chip using 0.18-/spl mu/m process technology to approximately a billion transistors on a chip using 0.10-/spl mu/m and finer process technologies, the microprocessor designer faces unprecedented Electronic Design Automation (EDA) challenges over the future generations of microprocessors. This paper describes the changes in the design environment that will be necessary to develop increasingly complex microprocessors. In particular, the paper describes the current status and the future challenges along three important areas in a design flow: design correctness, performance verification and power management.

Dense, performance directed, auto place and route

DAPR (for Dense Auto Place and Route) is Intels place and route system for standard cell-based random logic. DAPRs purpose is to produce dense, high-performance, design-rule clean double-layer metal layouts of the random logic modules within Intel custom application-specific standard product (ASSP) chips. DAPRs primary inputs are a schematic chip plan, a standard cell library, and a technology file. Optionally, DAPR can read placement files and performance directive files. Techniques used by Intels standard cell and route system to achieve densities comparable to those of full custom design. Methods are presented by which the placement and routing process is directed by performance objectives.<<ETX>>

A Variant of Parallel Plane Sweep Algorithm for Multicore Systems

Parallel algorithms used in Very Large Scale Integration physical design bring significant challenges for their efficient and effective design and implementation. The rectangle intersection problem is a subset of the plane sweep problem, a topic of computational geometry and a component in design rule checking, parasitic resistance-capacitance extraction, and mask processing flows. A variant of a plane sweep algorithm that is embarrassingly parallel and therefore easily scalable on multicore machines and clusters, while exceeding the best-known parallel plane sweep algorithms on real-world tests, is presented in this letter.

Scripting for EDA tools: a case study

Now to integrate EDA tools to enable interoperability and ease of use has been a very time-consuming and complicated job. Conventionally, each tool comes with a unique and simple set of commands for interactive use such as Sis, Vis, and Magic, but it lacks full programming capability of a scripting language. Also, it discourages further exploration to the underlying system functionality. Not only the code is hard to reuse, but also rapid prototyping of a new algorithm is impossible. A new algorithm may still take years to develop, which has to start from scratch and struggles between various formats. In this paper, we study and address how to easily integrate those application program interface (API)s into most popular scripting languages such as Tcl or Perl. This enables a full scripting or programming language capability into a tool, and most important of all, any tool can be interoperated over a uniform platform on an API level. Rapid prototyping of a new algorithm thus becomes much easier and faster. It also promotes software reuse. Many existing extension packages for the scripting languages can be therefore integrated such as Tk for graphic user interface (GUI), and CPAN collection for various Perl applications. From a standpoint of high software quality this approach also provides a very good vehicle for comprehensive testing of each API in an EDA tool.

Reinventing EDA with manycore processors

Faced with continually coping with Moores Law, computer-aided design (CAD) for integrated circuits is used to facing challenges in our ever-evolving design problem. Increasing device complexity is a perennial challenge and has led to several discontinuities in design methodology. Over the last decade deep submicron physical effects have significantly complicated the design process and required new efforts in design for manufacturability. With the emergence of multicore and manycore microprocessor systems we face a new type of challenge: Not only will our design object (the microprocessor systems themselves) take another leap in complexity, but for the first time in our industrys history we will need to fundamentally change the way we design and implement our software solutions as well, this panel a broad set of representatives at the front lines of addressing this challenge will outline how they plan to respond.

The deep sub-micron signal integrity challenge

Maintaining signal integrity in digital VLSI systems has become increasingly difficult due to the rising number of analog effects in deep sub-micron design. This paper provides an outline of the tutorial to be presented, as well as essential background material on the principle mechanisms behind signal integrity issues. The goal is to put forth a set of signal integrity challenges for future research and development.