Devesh Bhatt

SPI: an instrumentation development environment for parallel/distributed systems

This paper presents an overview of the Scalable Parallel Instrumentation (SPI) tool being developed at Honeywell. SPI provides a complete development and execution environment for developing real-time instrumentation functions for heterogeneous parallel/distributed systems. This includes: C-extensions and development tools for the event-action programming model, run-time support for transparent event-action execution on a heterogeneous distributed platform, and a library of primitives (actions) ranging from real-lime data collection, analysis to graphic display. Concurrent instrumentation functions can be flexibly parallelized/distributed over the heterogeneous platform to selectively analyze and display desired activity at the hardware, OS, IPC, and application levels. SPI is currently operational on a heterogeneous platform of SUN workstations and Intel Paragon.<<ETX>>

Towards Scalable Verification of Commercial Avionics Software

We describe a model-based approach for the automated verification of avionics systems that has been applied in Honeywell for the certification of complex commercial avionics applications, such as flight controls and engine controls. The approach uses a symbolic analysis framework for MATLAB Simulink models, utilizing range arithmetic to represent both test cases and equivalence-class transformations within a model of behavioral requirements. Backwards search from a set of desired test-case values within the model is combined with forward-directed simulation to resolve constraints and compute values in the visited paths, leading to a set of model-level input/output values that produce the test cases. We also describe a common design flaw that was uncovered in an early design phase by utilizing this approach. We argue that finding such designs flaws is extremely difficult by alternative methods such as directed or random simulations and traditional model checkers. Utilizing our approach, Honeywell has achieved better than 20 speedup on average in certification costs compared to traditional analysis and testing methods, while maintaining scalability on complex real-life problems.

Composable Code Generation for Model-Based Development

Many engineering and application domains, including distributed real-time and embedded (DRE) systems, are increasingly employing a graphical model-based development approach. However, the full potential of this approach has not yet been realized due to the complexity of automatically generating non-standard types of code. In this paper, we present a new framework for generating code that is referred to as composable code generation. Under this framework, code generators are not written as monolithic programs that are separate from their corresponding graphical models as has been the practice in the past. Instead, code generators are composed of modular entity-specific generation routines that are attached directly to modeling entities, their meta-data, or to collections of modeling entities. Code is built up by traversing the model, querying each entity that is encountered for a specific type of code generation routine and then executing each accessed routine. We describe this framework in detail and provide experimental results from a DRE application domain.

A methodology and toolset for the design of parallel embedded systems

Real-time embedded applications such as signal-processing, surveillance and tracking, data fusion, and automated target recognition need parallel processors to meet their performance requirements. Unfortunately the task of developing the application-software, which must not only make efficient use of the available parallelism but must also integrate the many algorithms that comprise it, is extremely difficult. Current software design methods, including object oriented design methods, do not help in this regard as they are geared primarily for the design of sequential software.This paper presents an overview of the Parallel Scalable Design Toolset (PSDT) being developed at Honeywell to support the design and development of real-time embedded parallel software. Software designers can use PSDT to graphically specify parallelism across collections of objects and within objects, and synchronization of data and control flows. They can also compose parallel subtasks into tasks that may in turn be a part of other tasks.PSDT can support different domain-specific parallelization paradigms. Each paradigm defines composition rules and constraints on inter- and intra-object parallelism. Since domain-specific paradigms add additional structure to the program, tools for parallelism analysis, partitioning, mapping, and code generation are able to produce near-optimum results.A prototype of the PSDT toolset is operational including a domain-specific paradigm for deterministic data-parallel periodic applications. Support for other domains and heterogenous processing architectures is being added.

A Design Notation and Toolset for High-Performance Embedded Systems Development

In traditional design methodologies, the system designer typically develops the application in a sequential paradigm almost to completion before addressing issues of parallelism and mapping to a heterogeneous architecture. As the architectural complexity of these applications increase, however, this process becomes too costly since implementation must be started anew after the design. The quality of the design also often suffers as a result. This is especially true for embedded applications, where the complexity lies within the system software and hardware architecture. We present a new methodology and toolset aimed at improving the system development process for high-performance embedded applications. The toolset provides a unified design representation from early design specification to integration—allowing for parallelism and synchronization specification in domain specific styles, and automating many process steps such as partitioning/mapping, simulation, glue-code generation, and performance analysis.

Quantifying Error Propagation in Data Flow Models

Model-based design is increasingly applied for the design and certification of flight-critical software. Software verification tools, however, have profound weaknesses in handling errors associated with signal values. Such errors can non-deterministically affect the performance and physical behavior of the cyber-physical system controlled by the software. We describe a scalable method that supports the analysis of signal value errors for applications specified as MATLAB Simulink data flow models. The approach explicitly propagates the errors associated with signal type and range bounds through the model and analyzes the possible effects of the errors on the cyber-physical systems behavior. We demonstrate the run time and scalability of the proposed approach on a set of avionics models developed for a commercial aircraft.

Implementing a distributed fault-tolerant embedded system in Ada

This paper presents the design and implementation experience of MEDS—an experimental distributed fault-tolerant system written in Ada that implements prototypes of some C3Ifunctions. MEDS implements distribution and fault-tolerance services such that application functions and data survive successive processor failures, and new or repaired processors can be added dynamically as additional resources. The design issues related to distribution/failure semantics, units of distribution, failure detection, reconfiguration, and recovery are discussed in the context of Ada. The design and implementation of these aspects of MEDS is presented and lessons learned from this experience are summarized.

DCT — A testbed approach to distributed systems research

The rationale and conceptual design 1s presented for the Distributed Computer Testbed (DCT), currently being developed at Honeywells Systems and Research Center. The DCT 1s a highly reconfigurable and Instrumented tool that will allow experimentation 1n a variety of distributed computing areas, ranging from performance evaluation of media access protocols to concept validation of distributed fault-tolerance strategies. Work 1s continuing on the detailed design and Implementation of DCT.

Auto Source Code Generation and Run-Time Infrastructure and Environment for High Performance, Distributed Computing Systems

With the emergence of inexpensive commercial off-the-shelf (COTS) parts, heterogeneous multi-processor HPC platforms have now become more affordable. However, the effort required in developing real-time applications that require high-performance and high input/output bandwidth for the HPC systems is still difficult. Honeywell Inc. has released a suite of tools called the Systems and Applications Genesis Environment (SAGE) which allows an engineer to develop and field applications efficiently on the HPCs. This paper briefly describes the SAGE tool suite, which is followed by a detailed description of the SAGE automatic code generation and run-time components used for COTS based heterogeneous HPC platform. Experiments were conducted and demonstrated to show that the SAGE generated glue (source) code with run-time executes comparably or within 75% efficiency to hand coded version of the Parallel 2D FFT and Distributed Corner Turn benchmarks that were executed on CSPI, Mercury and SKY compute platforms.

5th International Workshop on Embedded/Distributed HPC Systems and Applications (EHPC 2000)

The International Workshop on Embedded/Distributed HPC Systems and Applications (EHPC) is a forum for the presentation and discussion of approaches, research findings, and experiences in the applications of High Performance Computing (HPC) technology for embedded/distributed systems. Of interest are both the development of relevant technology (e.g.: hardware, middleware, tools) as well as the embedded HPC applications built using such technology.