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Dive into the research topics where Dhananjay Anand is active.

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Featured researches published by Dhananjay Anand.


IEEE Transactions on Smart Grid | 2015

A Hierarchical Incentive Arbitration Scheme for Coordinated PEV Charging Stations

Dhananjay Anand; Rupert Tull de Salis.; Yijie Cheng; James Moyne; Dawn M. Tilbury

Distribution utilities are becoming increasingly aware that their networks may struggle to accommodate a large number of plug-in electric vehicles (PEVs), especially at times of peak loading. In this paper, a centralized scheduling scheme is formulated to coordinate charging of a heterogeneous PEV fleet, which is then divided into load groups, each with a set of local objectives, constraints, and a decentralized control algorithm. Realistic energy tariffs are used to formulate probable “real-world” objectives for each load group, and a distributed dynamic program is used to regulate the net load of each load group. It is shown that charging coordination not only reduces peak network loads, but can also significantly reduce the customers PEV charging cost. Potential improvements from the perspective of communication and modeling are also highlighted by adopting a systematic approach to divide the PEV fleet into load groups.


design automation conference | 2018

An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems

Mohammadreza Mehrabian; Mohammad Khayatian; Ahmed Mousa; Aviral Shrivastava; YaShian Li-Baboud; Patricia Derler; Edward Griffor; Hugo A. Andrade; Marc Wiess; John C. Eidson; Dhananjay Anand

Formal specifications on temporal behavior of Cyber-Physical Systems (CPS) is essential for verification of performance and safety. Existing solutions for verifying the satisfaction of temporal constraints on a CPS are compute and resource intensive since they require buffering signals from the CPS prior to constraint checking. We present an online approach, based on Timestamp Temporal Logic (TTL), for monitoring the timing constraints in CPS. The approach reduces the computation and memory requirements by processing the timestamps of pertinent events reducing the need to capture the full data set from the signal sampling. The signal buffer size bears a geometric relationship to the dimension of the signal vector, the time interval being considered, and the sampling resolution. Since monitoring logic is typically implemented on Field Programmable Gate Arrays (FPGAs) for efficient monitoring of multiple signals simultaneously, the space required to store the buffered data becomes the limiting resource. The monitoring logic, for the timing constraints on the Flying Paster (a printing application requiring synchronization between two motors), is illustrated in this paper to demonstrate a geometric reduction in memory and computational resources in the realization of an online monitor.


great lakes symposium on vlsi | 2017

A Low-Cost GPS Spoofing Detector Design for Internet of Things (IoT) Applications

Tanvir Arafin; Dhananjay Anand; Gang Qu

The civilian Global Positioning System (GPS) is widely used for precise positioning, timekeeping, and synchronization in embedded systems. As a result, emerging digital infrastructure such as the Internet of Things (IoT) are dependent on GPS to locate and synchronize \textit{Things} in the network. From a security perspective, civilian GPS signals are vulnerable to malintent because they are not encrypted and can easily be spoofed. Several countermeasures have been proposed to detect GPS spoofing attacks, but most of them require extensive signal processing capabilities and additional electronic components to capture and analyze RF signals. These add-ons may not be available to IoT devices, and if present, they will affect the device\textquoteright s power budget significantly. Therefore, new techniques for spoofing detection and survival are required before integrating GPS receivers with IoT devices and other critical infrastructures where energy and computation power are limited. In this work, we propose a novel GPS spoofing detection scheme based on hardware oscillators. Our design depends on measuring the frequency drift and offset of a free-running crystal oscillator with respect to the GPS signals. In our secure GPS spoofing detector design the trust is intrinsic, \textit{i.e.}, the receiver only trusts the on-board free running local oscillator. Intrinsic properties of these oscillators exhibit a strong correlation with the authentic GPS signals and any anomaly in this measurement will indicate potential attacks on the received GPS signals. This proposed design is cost-effective, secure, backward compatible with existing receivers, and does not require additional RF circuitry or network connection with other clocks for detecting attacks.


information security | 2016

Multicast Delayed Authentication for Streaming Synchrophasor Data in the Smart Grid

Sérgio M. Câmara; Dhananjay Anand; Victoria Pillitteri; Luiz F. R. C. Carmo

Multicast authentication of synchrophasor data is challenging due to the design requirements of Smart Grid monitoring systems such as low security overhead, tolerance of lossy networks, time-criticality and high data rates. In this work, we propose inf -TESLA, Infinite Timed Efficient Stream Loss-tolerant Authentication, a multicast delayed authentication protocol for communication links used to stream synchrophasor data for wide area control of electric power networks. Our approach is based on the authentication protocol TESLA but is augmented to accommodate high frequency transmissions of unbounded length. inf TESLA protocol utilizes the Dual Offset Key Chains mechanism to reduce authentication delay and computational cost associated with key chain commitment. We provide a description of the mechanism using two different modes for disclosing keys and demonstrate its security against a man-in-the-middle attack attempt. We compare our approach against the TESLA protocol in a 2-day simulation scenario, showing a reduction of 15.82% and 47.29% in computational cost, sender and receiver respectively, and a cumulative reduction in the communication overhead.


advances in computing and communications | 2018

Conflict-driven Hybrid Observer-based Anomaly Detection

Zheng Wang; Farshad Harirchi; Dhananjay Anand; Chee Yee Tang; James Moyne; Dawn M. Tilbury


Special Publication (NIST SP) - 1500-08 | 2017

Timing Challenges in the Smart Grid

Jason Allnutt; Dhananjay Anand; Douglas Arnold; Allen R. Goldstein; YaShian Li-Baboud; Aaron Martin; Cuong Nguyen; Robert Noseworthy; Ravi Subramaniam


NASPI PMU Applications Requirements Task Force | 2017

Synchrophasor Data Quality Attributes and a Methodology for Examining Data Quality Impacts upon Synchrophasor Applications

Dhananjay Anand; Allen R. Goldstein; Alison Silverstein; Laurie E. Miller; Francis Tuffner; Yuri V. Makarov


Proceedings of the 47th Annual Precise Time and Time Interval Systems and Applications Meeting | 2016

Detecting GNSS Spoofing using a Network of Hardware Oscillators

Tanvir Arafin; Dhananjay Anand; Gang Qu


NIST Interagency/Internal Report (NISTIR) - 8077 | 2015

Investigation of PMU Response to Leap Second: 2015

Allen R. Goldstein; Dhananjay Anand; YaShian Li-Baboud


Archive | 2014

Networked Control Systems for Manufacturing

James R. Moyne; Dawn M. Tilbury; Dhananjay Anand

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YaShian Li-Baboud

National Institute of Standards and Technology

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James Moyne

University of Michigan

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Dawn M. Tilbury

National Taiwan University

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Ahmed Mousa

Arizona State University

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Chee Yee Tang

National Institute of Standards and Technology

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Edward Griffor

National Institute of Standards and Technology

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John C. Eidson

University of California

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