Dharmendra Singh Yadav

Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation

A novel device configuration is presented for doping-less charge plasma tunnel FET (TFET) for suppression of ambipolar nature with improved high-frequency figures of merit. For this, the drain electrode, which is used to induce n+ drain region, is separated into two sections of high and low work functions. The work function of the drain electrode section near to channel is considered relatively higher than other part for restricting the tunneling of holes at drain/channel interface for negative gate bias. This concept creates asymmetrical charge carrier concentration in the drain region, which increases the tunneling width at the drain/channel interface. Therefore, the proposed device offers better performance in terms of ambipolar current, parasitic capacitance, and RF parameters. In this regard, a comparative study of the proposed device is performed with conventional and dual-metal gate doping-less TFETs. Furthermore, the optimization of the length and higher work function of the drain electrode near to channel is discussed in detail for the proposed device. Apart from above-mentioned advantages, the doping-less nature of the proposed device provides fabrication simplicity and immunity against random dopant fluctuations in comparison with the physically doped TFET.

A Charge-Plasma-Based Dielectric-Modulated Junctionless TFET for Biosensor Label-Free Detection

To reduce the fabrication complexity and cost of the nanoscale devices, a charge-plasma concept is introduced for the first time to implement a dielectric-modulated junctionless tunnel field-effect transistor (DM-JLTFET) for biosensor label-free detection. The formation of p+ source and n+ drain regions in DM-JLTFET is done by the deposition of platinum (work function = 5.93 eV) and hafnium (work function = 3.9 eV) materials, respectively, over the silicon body. Furthermore, a nanogap cavity embedded within the gate dielectric is created by etching the portion of gate oxide layer toward the source end for sensing biomolecules. For this, the sensing capability of DM-JLTFET has been investigated in terms of variation in dielectric constant, charge density, length, and thickness of the cavity at different bias conditions. Finally, a comparative study between DM-JLTFET and MOSFET biosensor is investigated. The implementation of proposed device and all the simulations have been performed by using ATLAS device simulator.

Analysis of a Novel Metal Implant Junctionless Tunnel FET for Better DC and Analog/RF Electrostatic Parameters

Steep rise in the subthreshold slope, high current driving capability, and negligible ambipolarity are the major prerequisite conditions of tunnel FETs (TFETs) to make it applicable for Analog/RF circuit applications. Along with that, fabrication of physically doped TFETs is a major concern in device technology. In this context, this paper deals with junctionless TFET with a metal implanted in the oxide at the source/channel and drain/channel junctions to enhance its ON-current and reduce the ambipolar nature. The metal introduced at the source/channel junction generates abruptness and brings improvement in subthreshold slope, which increases the current driving capability of the device. Similarly, the metal implanted at the drain/channel junction widens the energy gap at the same junction to reduce the ambipolar behavior of the device. This also contributes to the enhancement of dc and analog/RF performance of the device. The selection of appropriate work function and length of the metal implanted at both the interfaces is important to maintain the improved ON-current and ambipolarity. This optimization gives idea of keeping the appropriate length, which provides direction toward practical feasibility at the experimental level.

Dual workfunction hetero gate dielectric tunnel field-effect transistor performance analysis

This paper features a study of DC and analog/RF response of dual work function hetero gate dielectric source pocket tunnel field-effect transistor (DW HGD SP TFET). For this, source pocket is used to enhance the tunneling of charge carrier results in increment in ON-state current. Further, the hetero gate dielectric is used to reduce the gate to drain capacitance which is a crucial parameter for RF performance determination. At the same time, work function engineering is useful to enhance the device performance in terms of ON-state current which influences the analog/RF performance but it is also increases the gate to drain capacitance which limits the RF parameters. Thus, combination of hetero gate dielectric and work function engineering provides an integrated effect on the device RF performance. In this regards, RF parameters such as transconductance, cutoff frequency, gain bandwidth product and transit time are calculated to analysis the device suitability in wireless communication.