Dhireesha Kudithipudi

Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions

Neural logic blocks (NLBs) enable the realization of biologically inspired reconfigurable hardware. Networks of NLBs can be trained to perform complex computations such as multilevel Boolean logic and optical character recognition (OCR) in an area- and energy-efficient manner. Recently, several groups have proposed perceptron-based NLB designs with thin-film memristor synapses. These designs are implemented using a static threshold activation function, limiting the set of learnable functions to be linearly separable. In this work, we propose two NLB designs-robust adaptive NLB (RANLB) and multithreshold NLB (MTNLB)-which overcome this limitation by allowing the effective activation function to be adapted during the training process. Consequently, both designs enable any logic function to be implemented in a single-layer NLB network. The proposed NLBs are designed, simulated, and trained to implement ISCAS-85 benchmark circuits, as well as OCR. The MTNLB achieves 90 percent improvement in the energy delay product (EDP) over lookup table (LUT)-based implementations of the ISCAS-85 benchmarks and up to a 99 percent improvement over a previous NLB implementation. As a compromise, the RANLB provides a smaller EDP improvement, but has an average training time of only ≈ 4 cycles for 4-input logic functions, compared to the MTNLBs ≈ 8-cycle average training time.

Reconfigurable N-level memristor memory design

Memristive devices have gained significant research attention lately because of their unique properties and wide application spectrum. In particular, memristor-based resistive random access memory (RRAM) offers the high density, low power, and low volatility required for next-generation non-volatile memory. The ability to program memristive devices into several different resistance states has also led to the proposal of multilevel RRAM. This work analyzes the application of thinfilm memristors as N-level RRAM elements. The tradeoffs between the number of memory levels and each RRAM elements reliability will be discussed. A metric is proposed to rate each RRAM element in the presence of process variations. A memory architecture is also presented which allows the number of memory levels to be reconfigured based on different application characteristics. The proposed architecture can achieve a write time speedup of 5.9 over other memristor memory architectures with 80% ion mobility degradation.

GALEOR: Leakage reduction for CMOS circuits

High performance and computational capability in the current generation processors are made possible by small feature sizes and high device density. To maintain the current drive strength and control the power dissipation in these processors, simultaneous scaling down of supply and threshold voltages is performed. High device density and low threshold voltages result in an increase in the leakage current dissipation. Large on chip caches are integrated onto the current generation processors which are becoming a major contributor to total leakage power. The proposed static power reduction technique, GALEOR (GAted LEakage TransistOR), reduces the leakage current flowing through the circuits. In the proposed leakage power technique, two gated leakage transistors are inserted between NMOS and PMOS circuitry of the existing circuit such that gates of the extra inserted transistors are connected to their respective drain regions. GALEOR technique was tested on standard cell gates and memory elements. Area overhead is minimized by eliminating the use of control logic to switch between the active and standby states. Performance overhead is increased due to the reduced output voltage swing.

Design and Analysis of a Neuromemristive Reservoir Computing Architecture for Biosignal Processing

Reservoir computing (RC) is gaining traction in several signal processing domains, owing to its non-linear stateful computation, spatiotemporal encoding, and reduced training complexity over recurrent neural networks (RNNs). Previous studies have shown the effectiveness of software-based RCs for a wide spectrum of applications. A parallel body of work indicates that realizing RNN architectures using custom integrated circuits and reconfigurable hardware platforms yields significant improvements in power and latency. In this research, we propose a neuromemristive RC architecture, with doubly twisted toroidal structure, that is validated for biosignal processing applications. We exploit the device mismatch to implement the random weight distributions within the reservoir and propose mixed-signal subthreshold circuits for energy efficiency. A comprehensive analysis is performed to compare the efficiency of the neuromemristive RC architecture in both digital(reconfigurable) and subthreshold mixed-signal realizations. Both Electroencephalogram (EEG) and Electromyogram (EMG) biosignal benchmarks are used for validating the RC designs. The proposed RC architecture demonstrated an accuracy of 90 and 84% for epileptic seizure detection and EMG prosthetic finger control, respectively.

A current-mode CMOS/memristor hybrid implementation of an extreme learning machine

In this work, we propose a current-mode CMOS/memristor hybrid implementation of an extreme learning machine (ELM) architecture. We present novel circuit designs for linear, sigmoid,and threshold neuronal activation functions, as well as memristor-based bipolar synaptic weighting. In addition, this work proposes a stochastic version of the least-mean-squares (LMS) training algorithm for adapting the weights between the ELMs hidden and output layers. We simulated our top-level ELM architecture using Cadence AMS Designer with 45 nm CMOS models and an empirical piecewise linear memristor model based on experimental data from an HfOx device. With 10 hidden node neurons, the ELM was able to learn a 2-input XOR function after 150 training epochs.

A Mathematical Formalization of Hierarchical Temporal Memory's Spatial Pooler

Hierarchical temporal memory (HTM) is an emerging machine learning algorithm, with the potential to provide a means to perform predictions on spatiotemporal data. The algorithm, inspired by the neocortex, currently does not have a comprehensive mathematical framework. This work brings together all aspects of the spatial pooler (SP), a critical learning component in HTM, under a single unifying framework. The primary learning mechanism is explored, where a maximum likelihood estimator for determining the degree of permanence update is proposed. The boosting mechanisms are studied and found to be only relevant during the initial few iterations of the network. Observations are made relating HTM to well-known algorithms such as competitive learning and attribute bagging. Methods are provided for using the SP for classification as well as dimensionality reduction. Empirical evidence verifies that given the proper parameterizations, the SP may be used for feature learning.

A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits

Hierarchical Temporal Memory (HTM) is a machine learning algorithm that is inspired from the working principles of the neocortex, capable of learning, inference, and prediction for bit-encoded inputs. Spatial pooler is an integral part of HTM that is capable of learning and classifying visual data such as objects in images. In this paper, we propose a memristor-CMOS circuit design of spatial pooler and exploit memristors capabilities for emulating the synapses, where the strength of the weights is represented by the state of the memristor. The proposed design is validated on a challenging application of single image per person face recognition problem using AR database resulting in a recognition accuracy of 80%.

Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures

In this paper, we propose a hybrid temperature sensing resistive random access memory (TSRRAM) architecture composed of traditional CMOS components and emerging memristive switching devices. The architecture enables each RRAM switching element to be used both as a memory bit and a temperature sensor. The TSRRAM is integrated into an Alpha 21364 processor as an L2 cache. Its accuracy and performance were simulated using a customized simulation framework. SPEC2000 benchmarks were used to generate thermal profiles in the Alpha processor core. Active and passive sensing mechanisms are also introduced as means for DTM algorithms to determine the thermal profile of the RRAM switching layer. The proposed architecture yielded a 2.14 K mean absolute temperature error during passive sensing, which is well within the useful range of dynamic thermal management (DTM) algorithms. Furthermore, the proposed design is shown to have only an 8 cycle performance overhead.

RRAM Motifs for Mitigating Differential Power Analysis Attacks (DPA)

Hybrid Resistive Random Access Memory(RRAM)/CMOS architectures offer several opportunities in the next generation high performance systems. These systems are vulnerable to side channel attacks(SPA), including Differential Power Analysis (DPA) attacks. An architecture with cryptoco processors integrated on a dedicated CMOS layer and the associated memory on the RRAM layer, can help mitigate the side channel attacks on these systems. In particular, we focus on the DPA attacks which can compromise the system performance, by statistically analyzing information of intermediate results in a cryptographic computation. In this paper we propose the use of RRAM to obscure the power signals that mitigate the DPA attacks. RRAM motifs are dynamically reconfigurable hardware crossbar structures that can be programmed on-the-fly in to a memory or sensing elements. We investigate a 4x64 RRAMmotif that can perform memory and sensing in tandem. Our analysis shows that we cannot easily distinguish between the memory access and sensing operations. Though the power dissipated in the best and worst case scenarios when reading from an RRAM motif varied by 9%, it does not provide any additional information on the specific access. Additionally, it was observed that the variations in the voltage and temperature of the RRAM generate noise in guessing the sub key and enhances the DPA resiliency of the system.

Variation tolerant 9T SRAM cell design

Nanoscale SRAM memory design has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. These issues oppose our ability to achieve stable bitcells and acceptable performance while maintaining density using the standard six-transistor(6T) circuit. To overcome these challenges, researchers have proposed different topologies for SRAMs with single-ended 8T, 9T, 10T bitcell designs. These designs improve the cell stability in the subthreshold regime but suffer from bit-line leakage noise, placing constraints on the number of cells shared by each bitline. In this paper, we propose a novel 9T SRAM cell topology which achieves both cell stability as well as prevents bit-line leakage. With the proposed 9T SRAM circuit, the read static noise margin is nearly twice that of conventional 6T SRAM circuit. Furthermore, the bitline leakage power consumption of the proposed 9T SRAM cell is reduced by up to 79\%, 76\% and 39\% when compared to the previously published 8T, 10T and 9T SRAM cells, respectively.