Diana Goehringer

Survey on Real-Time Networks-on-Chip

Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet the growing complexity of embedded applications with increasing computation parallelism. Particularly, real-time applications make out a significant portion of the embedded field. Networks-on-Chip (NoCs) are the backbone of communications in an MPSoC platform. However, the use of NoCs in real-time systems imposes complex constraints on the overall design. This paper discusses the challenges faced, when designing NoCs for real-time applications. Contributions in this area are surveyed on the level of guaranteed Quality-of-Service (QoS) support, adaptivity, and energy efficient techniques. Furthermore, the evaluation methodologies and experimental performance measurements of real-time NoCs are examined. This survey provides a comprehensive overview of existing endeavors in real-time NoCs and gives an insight towards future promising research points in this field.

Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview

The TULIPP project aims to simplify development of embedded vision applications with low-power and real-time requirements by providing a complete image processing system package called the TULIPP Starter Kit. To achieve this, the chosen high-performance embedded vision platform needs to be extended with performance analysis and power measurement features. The lack of such features plagues most embedded vision platforms in general and practitioners have adopted ad-hoc methods to circumvent the problem. In this paper, we describe four generic utilities that complement and refine the capabilities of existing platforms for embedded vision applications. Concretely, we describe a novel power measurement and analysis utility, a platform-optimized image processing library, a dynamic partial reconfiguration utility, and an utility providing support for using the real-time OS HIPPEROS within Xilinx SDSoC. Collectively, these utilities enable efficient development of image processing applications on the TULIPP hardware platform. In future work, we will evaluate the relative benefit of these utilities on key embedded image processing metrics such as frame rate and power consumption.

An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors

This paper presents a dynamic partial reconfigurable debugging system for embedded processors based upon a device start and stop (DSAS) approach [1]. Using this approach, a cycle-accurate debugging system can be dynamically configured to any embedded processor-based design at runtime. The debugging system offers lossless debugging because the design is stopped during data transfer to prevent the loss of data. The data can be transferred by any available data communication interface such as Ethernet or UART and can be viewed by open-source waveform viewers. The technique offers debugging without the need to re-synthesize the design by using the dynamic partial reconfiguration.

High-Level Synthesis of Software-Defined MPSoCs

The end of Dennard scaling led to the use of heterogeneous Multiprocessor Systems-on-Chip (MPSoCs) for a wide variety of applications such as image and signal processing. However, the complexity of programming and designing increases tremendously for heterogeneous MPSoCs. Besides high application requirements in terms of performance, area and energy consumption, short time-to-market is essential for the industry. As a result, a software productivity gap emerges. This paper presents an automatic development environment for heterogeneous MPSoCs that decreases the software productivity gap. Based on an MPI program, a heterogeneous MPSoC for FPGAs consisting of several MicroBlaze processors and accelerators is generated. The accelerators are developed by synthesizing functions using Vivado HLS that are marked with pragmas in the MPI program. To evaluate the environment in terms of performance and area, several use cases have been implemented on a Xilinx Zynq SoC. The design development phase and programming of heterogeneous MPSoCs are significantly simplified by the automatic development environment.

A call-up for circuit-switched NoCs in the Dark-Silicon Era

Networks-on-Chip (NoCs) are the backbone of communications in MPSoCs and future Many-Cores. The approaching thousand cores technology, together with the dark silicon era, put energy-efficiency on top of the challenges for future NoC-based multicore chips, where NoCs significantly contribute to the total chip power. This paper explores the use of circuit-switched (CS) NoCs as a low complexity energy-efficient solution for future platforms in the Dark-Silicon (Si) era. We present a thorough analysis for circuit-switched NoCs from hardware synthesis perspective at different threshold voltage (Vth) and supply levels. Based on this analysis, we further propose a Dark-si inspired multilayered-CS-NoC architecture. The proposed NoC is implemented as a mixed Vth double layered design, where each layer is optimized for a frequency level at a different supply voltage. Layer switching is explored on a per-router-port granularity level; links are either reserved on the fast or the slow layer based on the speed requirements, while the other layer is kept dark. The proposed NoC architecture is synthesized using Synopsys Design Compiler for SAED90nm technology. The obtained results show energy savings up to 34% compared to conventional single-layer single supply CS-NoCs.

Reconfigurable Multiprocessor Systems-on-Chip

Software Defined Radios (SDRs) require architectures with a high flexibility to support multi-mode and multi-standard receivers and transmitters. In addition, these architectures need to fulfill the contradicting requirements of high performance for processing high data rates and low power consumption to be deployable in mobile devices. As the market for SDR is evolving, a scalable and adaptive architecture is desired to be able to upgrade the architecture to provide the needed computing performance for future use cases. This chapter highlights the requirements of high flexibility, high performance, low power, and high scalability and presents a solution to fulfill these requirements using runtime reconfigurable Multi-Processor Systems-on-Chip (MPSoCs).

Session 3: Method and tools for system design

The four papers in this session present novel methodologies covering different aspects of system design. The first paper proposes a decentralized system-level security approach for task isolation on heterogeneous MPSoCs. A first prototype of the isolation unit is presented and realized in VHDL. The second paper focuses on low power design methods for system design based on lightweight dataflow programming techniques. The approach is evaluated by designing an FPGA-based accelerator for a deep neural network. The third paper presents a method for automated code generation for SIMD architectures based on constraint programming. The benefits of the approach are evaluated with DSP kernels and by comparing the results to hand-optimized code. Finally, the fourth paper proposes a methodology based on fuzzy logic for object image quality assessment (IQA) and compares it against other IQA approaches.

Reconfigurable Architectures Workshop (RAW)

In the last few years, we have seen a steady growth in exciting developments and applications in the field of Reconfigurable Computing. Many of these new developments are reported in these proceedings, in topics that include algorithms, architectures, tools, systems and applications. The technical program committee, which includes experts from the academia and industry around the world, has put together an excellent and stimulating program. The papers presented in these proceedings were selected from among 35 submissions. The technical program includes three regular sessions, one poster session, one keynote, and a new interactive session following each set of technical presentations. The aim of the interactive session is to provide the opportunity to all the authors to present a demo of their work to facilitate discussion and brainstorming with the RAW participants. We would like to express our sincere thanks to all those who have contributed to the success of the workshop. In particular, we would like to thank all the members of the program committee and reviewers for their valuable time and effort in the review process, and to provide constructive feedback to the authors. We also acknowledge the support of the IPDPS organizing committee and IEEE Computer Society in producing these proceedings. Finally, we thank all authors who contributed to this workshop, for submitting their manuscript and sharing their latest research results with the RAW community. We hope that you will find in these proceedings and workshop a valuable platform as well as source of information for your work.

Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012)

The 19th edition of the Reconfigurable Architectures Workshop (RAW 2012) was held in Shanghai, China, during May 21–22, 2012. All articles in this special section are extended versions of selected papers presented at RAW 2012. For final publication, they were peer reviewed to ensure that they are presented with the breadth and depth expected from this high-quality journal. There are a total of 3 articles in this special section. These articles present an interesting combination of theoretical and practical advances in the reconfigurable computing field. In “JITPR: A Framework for Supporting Fast Application’s Implementation onto FPGAs”, Sidiropoulos et al. propose a methodology, as well as the supporting toolset, designed to provide fast application implementation onto reconfigurable architectures with the usage of a Just-inTime (JIT) compilation framework. The efficiency of the introduced framework is demonstrated experimentally, showing a reduction of execution runtime compared to state-of-the-art approaches. “Virtual Networks Distributed Communication Resource Management” by Heisswolf et al. proposes the use of Virtual Networks (VN) to enable Quality of Service (QoS) for regions of Network-on-Chip-based (NoC) architectures. The Virtual Networks can be defined and configured during runtime, and the size of the VN region and assigned bandwidth can be adjusted depending on the application requirements. This concept targets packet-switched networks with virtual channels and is realized by an intelligent hardware unit that manages the virtual channel reservation process at system runtime. The proposed concept is implemented as a cycle-accurate SystemC simulation model. A hardware implementation demonstrates a low impact on area utilization and power consumption. In “A Comprehensive Performance Analysis of Virtual Routers on FPGA”, Ganegedara and Prasanna propose a new router virtualization approach for FPGAs called Virtualized Grouped (VG), which is based on routing table groupings. The new approach is compared against two state-of-the-art approaches called Virtualized Separate (VS) and Virtualized Merged (VM). Results show the benefits of the new approach in terms of a high scalability and a high throughput, while also having low memory requirements and power consumption. It is our pleasure to express our sincere gratitude to all who contributed in any way to produce this special section. We would like to thank all the reviewers for their valuable time and effort in the review process and for providing constructive feedback to the authors. We thank all authors who contributed to this special section for submitting their manuscript and sharing their latest research results. We hope that you will find in this special section a valuable source of information for your future research.