Diane T. Rover

Convolution on Splash 2

Convolution is a fundamental operation in many signal and image processing applications. Since the computation and communication pattern in a convolution operation is regular, a number of special architectures have been designed and implemented for this operator. The Von Neumann architectures cannot meet the real-time requirements of applications that use convolution as an intermediate step. We combine the advantages of systolic algorithms with the low cost of developing application specific designs using field programmable gate arrays (FPGAs) to build a scalable convolver for use in computer vision systems. The performance of the systolic algorithm of (Kung et al., 1981) is compared theoretically and experimentally with many other convolution algorithms reported in the literature. The implementation of a convolution operation on Splash 2, an attached processor based on Xilinx 4010 FPGAs, is reported with impressive performance gains.

The visual display of parallel performance data

Several performance visualization tools have demonstrated that helpful insights into parallel performance can be gained through graphical displays. However, much of this work has been experimental, specialized, and ad hoc. Evolving performance visualization into an integral, productive tool for evaluating parallel performance requires a more systematic, formal methodology that relates behavior abstractions to visual representations in a more structured way. We propose a high-level abstract model for the performance visualization process, explain its relationship to the most important concepts and principles of effective visualization practice, and illustrate the relationship between these concepts and our abstract model through specific case studies. We also discuss the relationship of performance visualization to general scientific visualization. >

Parallel performance visualization: from practice to theory

The visualization of performance data can offer helpful insights into the behavior of parallel systems. However, the visualization of parallel performance data presents challenges that have hindered its widespread application. In this article, we show how these challenges have motivated researchers to develop new tools and techniques. This development has in turn enabled the formulation of a coherent theory-i.e. a combination of an abstract model and of concepts and principles for parallel performance visualization. This theory gives a solid framework for the development of visualization technology. To overcome the problems of parallel performance visualization, tools must integrate performance evaluation models with performance displays. Also, users must be involved in the design and evaluation of these tools. >

Reflections on Teaching and Learning in an Advanced Undergraduate Course in Embedded Systems

An integrated series of courses on embedded systems has been developed at Iowa State University, Ames, spanning early undergraduate to graduate levels. The newest course in the series is CPRE 488: Embedded Systems Design, an advanced undergraduate course that fills a gap in the curriculum by providing system-level design experiences and incorporating new technology advancements. CPRE 488 development focused on lecture-lab integration and laboratory learning. Course and lab activities were designed using a learning model that captures lower-order and higher-order cognition levels of Blooms taxonomy. The learning experience in the laboratory is characterized using a technique to assess cognitive behavior. Results of applying the Florida Taxonomy of Cognitive Behavior are presented to summarize the depth of student learning and the opportunities for students to progress to higher-order thinking in the laboratory. After two years of experience with the new course, the authors reflect on the course design and outcomes, from both disciplinary and pedagogical viewpoints.

FPGA-based coprocessor for text string extraction

In document understanding, one of the early stages involves extracting text strings from a scanned image of the document. Often, the text is printed on a repetitive background of design patterns for visual effects. For recognition purposes, the text strings need to be extracted eliminating the background. Image morphology based algorithms have been proposed for this purpose. However, image morphology operations are compute intensive. We describe the design and synthesis of a high-performance coprocessor to meet the compute load. The algorithm has been synthesized for Splash 2, an attached processor on Sun hosts. The Xilinx Field-Programmable Gate Array (FPGA) based PEs are programmed using VHDL behavioral modeling. The design can run at near-ASIC speeds of /spl ap/22 MHz clock rate with effective timing of 3 milliseconds per 128/spl times/128 image frame and 3/spl times/3 structuring element. Compared with a SPARC station 20 timings of 1.5 sees, the present implementation has a speed advantage of the order of 500 times.

Visualizing the performance of SPMD and data-parallel programs

Abstract Observing the activities of a complex parallel computer system is no small feat, and relating these observations to program behavior is even harder. In this paper, we present a general measurement approach that is applicable to a large class of scalable programs and machines, specifically SPMD and data-parallel programs executing on distributed memory computer systems. The combined instrumentation and visualization paradigm, called VISTA, is based on our experiences in programming and monitoring applications running on an nCUBE 2 computer and a MasPar MP-1 computer. The key is that performance data are treated similarly to any distributed data in the context of the programming models and presented via a hierarchy of multiple views. Because of the data-parallel mapping of program onto machine, we can view the performance as it relates to each processor, processor cluster, or the processor ensemble and as it relates to the data structures of the program. We illustrate the utility of VISTA by example.

A Structured Approach to Instrumentation System Development and Evaluation

Software instrumentation is a widely used technique for parallel program performance evaluation, debugging, steering, and visualization. With increasing sophistication of parallel tool development technologies and broadening of application areas where these tools are being used, runtime data collection and management activities are growing in importance; we use the term instrumentation system (IS) to refer to components that support these activities in state-of-the-art parallel tool environments. An IS consists of Local Instrumentation Servers, an Instrumentation System Manager, and a Transfer Protocol. The overheads and perturbation effects attributed to an IS must be accounted for to ensure correct and efficient representation of program behavior, especially for on-line and real-time environments. Moreover, an IS is a key facilitator of integration of tools in an environment. In this paper, we define the primary components of an IS and their roles in an integrated environment, and classify ISs according to selected features. We introduce a structured approach to plan, design, model, evaluate, implement, and validate an IS. The approach provides a means to formally address domain-specific requirements. The modeling and evaluation processes are illustrated in the context of three distinctive IS case studies for PICL, Paradyn, and Vista. Valuable feedback on performance effects of IS parameters and policies can assist developers in making design decisions early in the software development cycle. Additionally, use of structured software engineering methods can support the mapping of an abstract IS model to an implementation of the IS.

Enhancing student learning in an introductory embedded systems laboratory

As technology advances, curriculum and laboratories are challenged to keep pace. This is especially true in computer engineering, where the range of technologies is constantly broadening and diversifying, as computer-based systems take on many forms and functions in everyday life. The question is, how should a contemporary curriculum train computer-engineering students for the vast scope of embedded system solutions? In this paper, the authors specifically consider where to begin, and ask, can powerful tools empower students to learn? They describe steps taken at Iowa State University to upgrade a sophomore level laboratory in embedded systems. They migrated from the popular 8-bit Motorola 68HC11 microcontroller as the core for a hardware-software development platform to the emerging 32-bit PowerPC 555 microcontroller. The 68HC11 is used in labs at numerous universities across the country and is supported with textbooks and educational packages. Conversely, the PowerPC is new to the academic environment and comes with a rich set of features and development tools. In this paper, they examine the similarities and differences between the laboratory platforms and their impact on student learning. They also identify strengths and weaknesses of the new laboratory environment, based on their own perspective and student feedback.

Software tools for complex distributed systems: toward integrated tool environments

The demands on software tools for the design and testing of complex distributed systems are considerable. An environment that integrates domain-specific and commercial off-the-shelf tools and that supports rapid prototyping of application-specific tools can greatly increase the functionality and usability of such tools. We look at distributed computing systems as complex systems, focusing on two contemporary examples, and present an overview of online monitoring and dynamic analysis tools that support the design and test of such systems. To provide a specific example of integration and rapid prototyping, we describe an integrated tool environment that we have targeted at the types of complex systems addressed in this article.

Perspectives on learning in a capstone design course

A new course learning model was developed for our capstone design course in computer engineering, ECE 482-Capstone: Computer System Design. It has been delivered during six semesters, each providing a set of new experiences and an array of lessons learned. Students, employers and educational researchers have recognized the benefits of the course. Despite the positive outcomes, key questions and obstacles remain that impact sustainable reform in the capstone design experience. We chronicle the experiences and lessons from the perspectives of the faculty and students involved with the course. We focus on the learning model, including its implementation, adaptation, impact and perception.