Didier Belot

A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications

This paper presents a fully integrated 60GHz transceiver module in a 65nm CMOS technology for wireless high-definition video streaming. The CMOS chip is compatible with the WirelessHD™ standard, covers the four channels and supports 16-QAM OFDM signals including the analog baseband. The ESD-protected die (9.3mm²) is flip-chipped atop a High Temperature Cofired Ceramic (HTCC) substrate, which receives also an external PA and the emission and reception glass-substrate antennas. The module occupies an area of only 13.5×8.5mm². It consumes 454mW in receiver mode and 1.357W in transmitter mode (357mW for the transmitter and 1W for the PA).

A high-performance CMOS-SOI antenna switch for the 2.5-5-GHz band

Taking full advantage of the high resistivity substrate and underlying oxide of silicon-on-insulator (SOI) technology, a high-performance CMOS single-pole double-throw (SPDT) T/R switch for Bluetooth class-II applications has been designed and fabricated in a partially depleted 0.25-/spl mu/m SOI process. To compare the influence on losses and isolation of the substrate resistivity, the switch has been integrated above standard and high resistivity (20 /spl Omega//spl middot/cm and 1 k/spl Omega//spl middot/cm) substrates. The switch over the standard resistivity substrate exhibits 1 dB of insertion loss and 45dB of isolation at 2.4 GHz. With the high resistivity substrate, the overall performances are strongly improved until 0.7-dB insertion loss and a 54-dB isolation at 2.4 GHz. At 5 GHz, the switch over the high resistivity substrate keeps insertion loss and isolation at 1 and 46 dB, respectively. In both cases, the measured 1-dB input compression point is 12 dBm. The targeted Bluetooth class-II specifications have been fully fitted.

Nanoscale CMOS Transceiver Design in the 90–170-GHz Range

This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately + 2 dBm and a phase noise of -90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1/f noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

A G/sub m/-C low-pass filter for zero-IF mobile applications with a very wide tuning range

A third-order G/sub m/-C Butterworth low-pass filter implementing G/sub m/-tuning and G/sub m/-switching to maximize the tuning range is described. This filter is intended to be used as a channel-selection/anti-aliasing filter in the analog baseband part of a zero-IF radio receiver architecture for multimode mobile communications. Its G/sub m/-switching feature allows extending the tuning range and adapting the power consumption. The filters cutoff frequency ranges from 50 kHz to 2.2 MHz. An Input IP3 of up to +18 dBV/sub p/ is achieved, for a total worst-case power consumption of 7.3 mW for both I and Q paths, and an effective area of less than 0.5 mm/sup 2/ in a 0.25-/spl mu/m SiGe BiCMOS process. A new figure of merit is introduced for comparison of published low-pass tunable filters including noise, linearity, and tuning range.

A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS

This paper presents a 1.2 V, 100 mW, 140 GHz receiver with on-die antenna in a 65 nm General Purpose (GP) CMOS process with digital back-end. The receiver has a conversion loss of 15-19 dB in the 100-140 GHz range with 102 GHz LO, and occupies a die area of only 580 mum times 700 mum including pads. The LNA achieves 8 dB gain at 140 GHz, 10 GHz bandwidth, at least -1.8 dBm of saturated output power, and maintains 3 dB gain at 125 degC. The on-chip antenna, which meets all density fill requirements of 65 nm CMOS, has -25 dB gain, and occupies 180 mum times 100 mum of die area. Additionally, design techniques which maximize the millimeter-wave performance of CMOS devices are discussed.

A SiGe:C BiCMOS WCDMA zero-IF RF front-end using an above-IC BAW filter

The feasibility of a fully integrated RF front-end using an above-IC BAW integration technique is demonstrated for WCDMA applications. The circuit has a voltage gain of 31.3dB, a noise figure of 5.3dB, an in-band IIP3 of -8dBm and IIP2 of 38dBm, with a total power consumption of 36mW. The BAW filter area is 0.45mm/sup 2/ and the total circuit area including the BAW filter is 2.44mm/sup 2/.

A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications

This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. This frequency synthesizer is fully compliant with IEEE 802.15.3c normalization [1–4]. This PLL delivers a quadrature LO signal around 20GHz and a differential LO signal around 40GHz and has 17.9% tuning range. The wide tuning range of 17.9% permits to cover the full IEEE 802.15.3c band with industrial margin. The phase noise is −100dBc/Hz at 1MHz offset and the total power dissipation is only 80mW including the output buffers and amplifiers. Short-range wireless multi-Gb/sec communication systems use the mm-wave band of 57GHz to 66GHz, according to the IEEE 802.15.3c normalization. The frequency synthesis is one of the key elements for these transceivers. Indeed, one must take into account the antagonist tradeoff between large band tuning range of the frequency synthesizer and phase noise performance. In transceivers using super-heterodyne architecture with double conversion, the frequency synthesizer signal fLO can be equal to 2fRF /3 and fRF /3. In this case, to cover the four channels of the IEEE 802.15.3c normalization, the frequency synthesizer has to deliver a first local oscillator (LO) signal between 19.44GHz and 21.6GHz and a second LO signal between 38.88GHz and 43.2GHz, respectively. This architecture offers a good trade off between the required large frequency tuning range (≫15%) and low phase noise (≪−95dBc/Hz).

A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS

CMOS circuits operating up to 60GHz have been demonstrated to satisfy the market demand for high data rates and frequency bandwidths [1–6]. However, 60GHz products need an improvement in power performance as well as transistor reliability for large signal operation. Moreover, Class-A or Class-AB power amplifiers (PA) are mandatory to overcome the difficulty of the limited maximum available gain (MAG) at mm-Wave frequencies [1–6] and the high linearity required by the OFDM modulation used in the IEEE 802.15.3c wireless HD standard. That means a maximum drain-source voltage swing of twice the DC voltage, which introduces specific design or supply voltage in order to respect reliability constraints [1,7]. This paper describes a PA with 8 power-combined ways and cascode topology in a 7-metal-layer 65nm CMOS process which covers the full band for 60GHz wireless applications. The presented circuit operates at a standard supply of 1.2V or 1.8V, and achieves a saturated output power of 16.6dBm and 18.1dBm respectively. The measured output power is high for CMOS while insuring reliability for time-dependent dielectric breakdown (TDDB) and hot-carrier-injection (HCI) degradation.

Design for millimeter-wave applications in silicon technologies

This paper presents the potentialities of advanced BiCMOS and CMOS technologies for millimeter-wave applications. To begin, the target applications in these frequency bands are presented: from automotive cruise control radars to wireless links. Then, a large overview of the technological offer to address these applications is presented: SiGe BiCMOS, nanometer bulk and SOI CMOS technologies. This work focuses both on active and passive devices (BEOL) behavior to suit for design above 20 GHz. The paper continues with a presentation of several solutions for integrated circuits on the presented topic: front-end receiver blocks, transmission blocks and frequency synthesis solutions. An overview of state of the art silicon circuits is given. As a conclusion, perspectives regarding future challenges in terms of system integration and applications are discussed.

0.13/spl mu/m CMOS SOI SP6T antenna switch for multi-standard handsets

This paper presents the design of a single pole 6 throw antenna switch able to manage all the four GSM standards, i.e. 850-900-1800-1900 MHz. The switch has been integrated in a 0.13mum CMOS SOI process with high resistivity substrate and a thick oxide (50Aring) option. The use of high resistivity substrate allows a good loss (IL)-isolation trade-off: IL is kept in the range of 0.55-0.8 dB for the RXs and at 0.7 dB for the TXs, while isolation varies from 40 dB at 900 MHz to 30 dB at 1900 MHz. Power handling capability is well compatible with GSM standards since an ICP0.1dB of 36 dBm has been measured and harmonics distortion is below -39 dBm for an input power of 34 dBm. Robustness to antenna mismatching condition has been successfully demonstrated up to a VSWR of 10:1. The chip size is of 1.23 mm2 and the power consumption is below 10muA and 0.5 mA respectively in stand by mode and during switching, under 2.5 voltage supply