Didier Cottet

Simulation of the non-idealities in current sharing in parallel IGBT subsystem

The parallel connection of the power semiconductors is used to achieve higher current and higher output power. Small differences in the device characteristics can cause significant differences in the current sharing. Another well known reason for the current imbalance is the asymmetry of the paralleling impedances. These two design aspects are referenced in this paper. A simulation case study is used to illustrate the effect of differences in the power semiconductors and in the paralleling busbars. Simulation results are compared with respective experimental results.

Investigation on current density limits in power printed circuit boards

Joule heating of copper traces is known as one major failure cause in high current printed circuit boards. The paper summarizes tests that were performed to investigate the actual failure mechanisms related to high current densities. The current values at which the boards failed show how conservative the present design rules for traces and via holes are. An electrothermal modeling method for printed circuit board is proposed for further analysis of current and temperature distributions in different layout configurations and under different load conditions.

The Corrugated P-Base IGCT - a New Benchmark for Large Area SQA Scaling

A 91 mm diameter IGCT with extraordinary safe operating area (SOA) is presented in this paper. The power density at turn-off reached values as high as 700 W/cm2, which is twice the previously reported SOA limit for devices with a comparable diameter. The improvement was achieved by masking one of the p-base diffusions, giving the p-base a corrugated appearance as well as improving the gate circuit.

Active lifetime extension — Demonstrated for voltage source converters

Many voltage source converters have no redundant power components (e.g. IGBT modules) built in. Therefore if one power component fails, the converter stops working. Here we introduce a generic approach that takes advantage of the inherent redundancies of voltage vectors in multilevel converters in order to actively extend the lifetime of converters. When detecting increased stress of one IGBT module, the switching strategy is altered in order to reduce the load of that particular IGBT module. The active lifetime extension (ALE) switching strategy aims to balance the remaining life of all IGBT modules at all times. In such way the lifetime of the converter is maximized.

Modeling of large bus bars using PEEC method and circuit level simulators

This paper presents an efficient modeling approach for large bus bar systems in power electronic frequency converters using partial element equivalent circuit (PEEC) method and circuit-level simulations. Several acceleration methods have been applied to improve the computational speed and memory efficiency. The approach is verified against measurements, and used to analyze the impact of the stray impedance of bus bars on the electromagnetic and circuit behavior of a static frequency converter system.

Electromagnetic simulation and design of complex, planar bus bars for multi-level, high power converters

In this paper, a state-of-the-art electromagnetic PEEC simulator is used in combination with task specific modeling methods to simulate a complex, planar bus bar of an actual multi-level, high power converter. The task specific modeling method proposed consists of defining the exact objective of the simulation and to make use of the bus bars typical AC and DC impedance characteristics in terms of inductance and resistance when defining the mesh. This way, the simulation effort is significantly reduced, thus allowing efficient layout changes based on simulated current densities and magnetic field patterns. For the critical commutation loop of the case study bus bar used in this work, the stray inductance was reduced by about 15 % with only minor layout modifications and minimal simulation effort.

Investigation on Via Arrangements for the Thermal Management of High Current PCBs

Joule heating of copper traces and vias in high current PCBs can significantly deteriorate the reliability of power electronics products. Optimization of the PCB layout is therefore fundamental to guarantee the thermal performance of a converter. This paper investigates the temperature distribution of copper traces and through via holes, when number and disposition of parallel vias are changed in a standard PCB.