Dieter Kaiser

Grayscale lithography: 3D structuring and thickness control

Grayscale lithography has become a common technique for three dimensional structuring of substrates. In order to make the process useful for manufacturing of semiconductor and in particular optoelectronic devices, high reproducible and uniform final film thicknesses are required. Simulations based on a calibrated resist model are used to predict customized process parameters from pixel layout to 3d substrate patterning. Multiple, arbitrary resist heights are reached by using i-line lithography. Scalable and uniform transfer of discrete step heights into oxide are realized by multiple alternating high selective resist and oxide (MASO) etch. Requirements and limitations of reliable 3D film thickness and uniformity control within a CMOS fabrication environment are being discussed.

Automatic CD-SEM offline recipe creation for OPC qualification and process monitoring in a DRAM pilot-fab environment

In our work we discuss two approaches of offline CD-SEM recipe creation for both OPC qualification wafers and the introduction of new products to the manufacturing line using the Applied Materials OPC Check and Offline Recipe Editor (ORE) applications. We evaluate the stability of the offline created recipes against process variations for different OPC test layouts as well as for production measurements on multiple lots per week and compare the results to the performance of recipes created directly on the tool. Further, the success rate of recipe creation is evaluated. All offline recipes have been generated in advance of wafer availability using GDS data. The offline created recipes have shown pattern recognition success rates of up to 98% and measurement success rates of up to 99% for line/space as well as for contact-hole (CH) measurements without manual assists during measurement. These success rates are in the same order of magnitude as the rates typically reached by an experienced CD-SEM engineer creating the recipes directly on the tool.

Manufacturability of ILT patterns in low-NA 193nm environment

With escalating costs of higher-NA exposure tools, lithography engineers are forced to evaluate life-span extension of currently available lower-NA exposure tools. In addition to common resolution enhancement techniques such as off-axis illumination, edge movement, or applying sub-resolution assist features, Inverse Lithography Technology (ILT) tools available commercially at this moment offer means of extending current in-house tool resolution and enlarging process window for random as well as periodic mask patterns. In this paper we explore ILT pattern simplification procedures and model calibration for a range of illumination conditions. We study random pattern fidelity and critical dimension stability across process window for 65nm contact layer, and compare silicon results for both conventional optical proximity correction and inverse lithography techniques.

Consideration of VT5 etch-based OPC modeling

Including etch-based empirical data during OPC model calibration is a desired yet controversial decision for OPC modeling, especially for process with a large litho to etch biasing. While many OPC software tools are capable of providing this functionality nowadays; yet few were implemented in manufacturing due to various risks considerations such as compromises in resist and optical effects prediction, etch model accuracy or even runtime concern. Conventional method of applying rule-based alongside resist model is popular but requires a lot of lengthy code generation to provide a leaner OPC input. This work discusses risk factors and their considerations, together with introduction of techniques used within Mentor Calibre VT5 etch-based modeling at sub 90nm technology node. Various strategies are discussed with the aim of better handling of large etch bias offset without adding complexity into final OPC package. Finally, results were presented to assess the advantages and limitations of the final method chosen.

Revival of grayscale technique in power semiconductor processing under low-cost manufacturing constraints

Grayscale lithography is a well-known technique for three dimensional structuring of a photo sensitive material. The 3D structuring of the photoresist is performed by a spatially variable exposure. Pixelated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. Within power semiconductor processing, grayscale techniques could beneficially be applied in different process steps. Several ideas come to mind for process simplification, alternative integration scheme and more, e.g. the realization of 3D resist patterns for implant applications in order to control the doping depth and profiles and their influence on device parameters. In order to make the grayscale process useful for manufacturing of semiconductor devices it is necessary to master and consider the inherent process variability. Lithographic simulation is used to optimize the sub-resolution photo-mask features and to predict the final resist shape and its variability. Device simulation for a DMOS device, used in our 130nm technology node, shows that the device performance would benefit from an attenuation of the implant dose in the center of the device, which could be achieved by creating a resist island with reduced resist thickness in the center of the drawn implant opening of the DMOS device. In order to achieve the desired target geometry of the implant resist mask, simulations with Sentaurus Lithography have been performed resulting in a suitable mask design and lithographic process. We will demonstrate the development of the grayscale litho-process based on the needs of an implant scheme that is going to be used for a DMOS device, with respect to process stability and achieved resist mask dimensions.

3D lithography for implant applications

In this paper we describe an approach for the realization of 3D resist patterns for implant applications, highlighting the opportunities of controlling doping depth and profiles and their influence on device parameters. We choose a grayscale litho process, where the 3D structuring of the photoresist is done by a spatially variable exposure. Pixilated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. The variable transmittance values result in different resist film thicknesses after development. Up to 20 different resist film thicknesses are obtained within a single exposure shot. This enables spatial patterning of the implant depth and accordingly various novel approaches for device optimization.

Source and mask optimization applications in manufacturing

Among available lithography resolution enhancement techniques the Selective Inverse Lithography (SILT) approach recently introduced by authors [1] has been shown to provide the largest process window on lower-NA exposure tools for 65nm contact layer patterning. In present paper we attempt to harness the benefits of source mask optimization (SMO) approach as part of our hybrid RET. The application of source mask optimization techniques further extends the life-span of lower-NA 193nm exposure-tools in high volume manufacturing. By including SMO step in OPC flow, we show that model-based SRAF solution can be improved to approach SILT process variation (PV) band performance. Additionally to OPC, the complexity of embedded flash designs requires a high degree of exposure tool matching and a lithography process optimized for topographically different logic and flash areas. We present a method how SMO can be applied to scanner matching and topography-related optimization.