Dietmar Tutsch

Generating Systems of Equations for Performance Evaluation of Multistage Interconnection Networks

Multistage interconnection networks (Banyan networks) are frequently proposed as connections in multiprocessor systems, in ATM switches, or in Gigabit Ethernet switches. There exist several analytical models for evaluating the performance of such networks. Analytical models are much faster for this purpose than simulation. On the other hand, the development of an analytical model is very time-consuming. In this paper, we present a method for the automatic and fast generation of an analytical network model. The generated analysis handles networks of arbitrary size, arbitrary switching element sizes, arbitrary buffer lengths in each network stage, an arbitrary (but uniform) traffic pattern, and an arbitrarily chosen network load. The arbitrary traffic patterns include multicast traffic, which has not been considered by former models.

MLMIN: A multicore processor and parallel computer network topology for multicast

In future, multicore processors with hundreds of cores will collaborate on a single chip. Then, more advanced network-on-chip (NoC) topologies will be needed than todays shared busses for dual core processors. Multistage interconnection networks, which are already used in parallel computers, seem to be a promising alternative. In this paper, a new network topology is introduced that particularly applies to multicast traffic in multicore systems and parallel computers. Those multilayer multistage interconnection networks are described by defining the main parameters of such a topology. Performance and costs of the new architecture are determined and compared to other network topologies. Network traffic consisting of constant size packets and of varying size packets is investigated. It is shown that all kinds of multicast traffic particularly benefit from the new topology.

Formal models for multicast traffic in network on chip architectures with compositional high-level Petri nets

Systems on chip and multicore processors emerged for the last years. The required networks on chips can be realized by multistage interconnection networks (MIN). Prior to technical realizations, establishing and investigating formal models help to choose best adequate MIN architectures. This paper presents a Petri net semantics for modeling suchMINs in case of multicast traffic. The new semantics is inspired by high-level versions of the Petri box algebra providing a method to formally represent concurrent communication systems in a fully compositional way. In our approach, a dedicated net class is formed, which leads to three kinds of basic nets describing a switching element, a packet generator, and a packet flush. With these basic nets, models of MINs of arbitrary crossbar size can be established compositionally following their inductive definition. Particular token generation within these high-level nets, as for instance, random load, yields an alternative approach to the use of stochastic Petri nets as in previous studies. The simulation of the models under step semantics provides a basis for performance evaluation and comparison of various MIN architectures and their usability for networks on chips. Particularly, multicast traffic patterns, which are important for multicore processors, can be handled by the new model.

Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions

Chip multiprocessors (CMPs) have become the center of attention in recent years. They consist of multiple processor cores on a single chip. These cores are connected on-chip by a bus or, if many cores are involved, by an appropriate network. To investigate how a multicore processor behaves dependent on the chosen network-on-chip topology, a corresponding model must be established for performance evaluation. Modeling and simulating the entire system would lead to high model complexity. Thus, it is more reasonable to exclude the cores and to simply model stochastically the detached network. The cores are replaced by traffic generators which must provide reasonable CMP traffic. It usually consists of multicasts and a particular spatial distribution. Because the traffic is not known exactly, both multicasts and spatial traffic are described as stochastic distributions for model input. The easiest way is to specify the spatial distribution of the traffic and the kind of multicasts independently of each other. However, not all multicast distributions can be achieved with a particular desired spatial distribution and vice versa. It is therefore important to check for the compatibility of the spatial distribution and the multicasts that the modeler is willing to investigate. Such a compatibility check is provided by the algorithm presented in this paper. It prevents inconsistent traffic parameters while modeling.

Quantile Estimation for Performance Measures in Network Simulations with CINSim

We consider a closed queueing network of generalized queues with customers and signals. each queue has an infinite capacity and one server. the service time is exponential. after its service completion a customer moves to another queue and may become a signal. when the signal enters a non empty queue it vanishes while it resets the queue when it enters an empty queue. we prove that the steady state-distribution for such a closed network of queues has a product form solution. to the best of our knowledge it is the first closed network of generalized queues with product form solution. we also consider a more complex system where the reset acts upon a set of queues rather than a single one. we also prove that the steady-state distribution exists and has a product form.

An Analyzable On-Chip Network Architecture for Embedded Systems

The increasing integration level of modern and forthcoming Integrated Circuits (ICs) allows the implementation of complex systems on a single chip (System-on-Chip – SoC) [1]. To reduce time to market in the design flow of chip development prefabricated components (known as Intellectual Property – IP) are used. IP cores can be CPUs, memory blocks, signal processing units, etc. Simplified, the design of new complex customized ICs often represents a composition of IP cores. The main task of a chip designer is the selection, parameterization, and interconnection of the different cores. Currently, the interconnection between the IP cores are realized with either dedicated point-to-point interconnections or standardized system buses. Dedicated point-to-point connections are only manageable and economically feasible in smaller systems. With increasing complexity, it is not possible to connect every core with dedicated wires. Buses, on the other hand, are an example for shared communication resources. The system design with a standardized bus and IP cores with an interface to the bus in question, becomes much simpler. Examples for on-chip buses are IBM Core Connect, AMBA-Bus by ARM, and the VCI-Standard by the VSIA. However, as a drawback, buses are not scalable for larger designs. The communication between cores becomes the performance bottleneck of the system. SoC design tends to replace buses with packet-switched interconnection networks [5]. The architecture of switched on-chip networks are similar to

Buffer Design in Delta Networks

Multistage interconnection networks (MINs) are frequently proposed as connections in multiprocessor systems or network switches. Delta networks are a subset of MINs and are investigated in this paper. A generator is used to set up automatically systems of equations modeling such delta networks. The model allows to calculate analytically the performance of MINs, e.g. for various buffer sizes. Comparing different buffer sizes helps to determine the optimal size for a given traffic pattern including multicast traffic. The influence of the buffer size on the network throughput and delay for small and large switching elements is also examined. The optimal network parameter choice for a given traffic pattern can be found.