Dietrich Maiwald

Rapid Training of a Voiceband Data-Modem Receiver Employing an Equalizer with Fractional-T Spaced Coefficients

Fast initial training of a voiceband data-modem receiver which employs an equalizer with fractionl- T spaced coefficients is presented. The modem receiver performs rapid gain acquisition, and monitors the equalizer delay line for the presence of a periodic training signal whose period is equal to the length of the equalizer delay line. Testing for periodicity is combined with estimating carrier-frequency offset. Once a full period of the training signal has been obtained, the equalizer coefficients are computed by spectral division, and coefficient centering is performed. The receiver then proceeds in a reference-directed mode until the end of the training signal is detected. In the paper, algorithms for rapid gain acquisition and the detection of a cyclic training signal in the presence of noise and carrier-frequency offset are presented. Cyclic training of an equalizer with fractional- T spaced coefficients is derived. It is shown that the equalizer coefficients can be computed efficiently by spectral division. Coefficient centering, carrier-phase and symbol synchronization, reference-directed training, and the transition to data mode are described. Finally, measurement results for an experimental 2400 baud modem using an equalizer with 64 T/2 -spaced coefficients are given. The modem achieves a startup time of 20 ms on a Bell 3002 unconditioned leased line.

Architecture of a digital signal processor

A digital signal processor (DSP) is described which achieves high processing efficiency by executing concurrently four functions in every processor cycle: instruction prefetching from a dedicated instruction memory and generation of an effective operand, access to a single-port data memory and transfer of a data word over a common data bus, arithmetic/logic-unit (ALU) operation, and multiplication. Instructions have a single format and contain an operand, index control bits, and two independent operation codes called “transfer” code and “compute” code. The first code specifies the transfer of a data word over the common data bus, e.g., from data memory to a local register. The second determines an operation of the ALU on the contents of local registers. A fast free-running multiplier operates in parallel with the ALU and delivers a product in every cycle with a pipeline delay of two cycles. The architecture allows transversal-filter operations to be performed with one multiplication and ALU operation in every cycle. This is accomplished by a novel interleaving technique called ZIP-ing. The efficiency of the processor is demonstrated by programming examples.

Radio Protocol Architecture of the CODIT UMTS System

This paper describes the protocol architecture of the radio interface of the CODIT Universal Mobile Telecommunication System (UMTS). It outlines the structure of layer 2 and 3 of the radio protocol stack, includes an overview of the network reference model, and discusses some CODIT testbed aspects.

An adaptive equalizer with significantly reduced number of operations

In adaptive equalization, the coefficients of a transversal filter are automatically adjusted according to a minimum mean-square error criterion. The convolution for the filter process and the cross-correlation in the coefficient-adjustment algorithm require a large number of arithmetic operations. This paper describes an equalizer for complex signals in which filtering and coefficient adjustment are performed in the frequency domain employing Winograds Fourier transform algorithms. Compared to the time-domain implementation, the number of multiplications is reduced by typically a factor five without increasing the number of additions. A fast initialization algorithm will be presented. In contrast to earlier work, the convergence behavior will be shown for random data signals transmitted over realistic telephone channels.

The SP16 signal processor

The SP16 processor executes typical signal-processing tasks efficiently by overlapping in each processor cycle four functions: instruction prefetching, data-memory access and transfer of one data word over a single data bus, ALU operation, and multiplication. Despite SP16 being a one-address machine with a single data bus, it can perform filter operations with a multiplication and ALU operation in every processor cycle.