Dihu Chen

A power-area-efficient, 3-band, 2-RX MIMO, TD-LTE receiver with direct-coupled ADC

In this work, a power-area-efficient, 3-band, 2-RX MIMO, and TD-LTE backward compatible with the HSPA+, HSUPA, HSDPA, and TD-SCDMA CMOS receiver is presented and implemented in 0.13-µm CMOS technology. The continuous-time delta-sigma A/D converters CT i¾?Σ ADCs are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti-aliasing filters between RX front-end and ADCs in conventional structures. The strong adjacent channel interference without low-pass filter attenuation is handled by proper gain control. A low-power small-area solution for excess loop delay compensation is implemented in the CT i¾?Σ ADC. At 20MHz bandwidth, the CT i¾?Σ ADC achieves 66dB dynamic range and 3.5dB RX chip noise figure is measured. A maximum of 2.4dB signal-to-noise ratio degradation is measured in all the adjacent channel selectivity ACS and blocking tests, demonstrating the effectiveness of the strategy against the low-pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171mW at 2-RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD-LTE receiver. Copyright

A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration

A delta-sigma (ΔΣ) phase locked loop (PLL) transmitter with an efficient modulation bandwidth calibration technique is proposed in this paper. With the proposed technique, the digital-analog mismatch between digital pre-emphasis filter and PLL is calibrated. The loop filter RC variation is tracked in the first place, and then the variation of the loop gain is calibrated by sensing the magnitude differences of the modulator between DC and ten times of the loop bandwidth. The proposed transmitter has been implemented in 0.18- μm CMOS technology for GSM/GPRS application. Measurement results show that the maximum RMS phase error of the proposed transmitter is 0.8 °. In addition, the measured calibration accuracies for RC and loop gain variations are 0.5% and 0.8%, respectively. By reusing the PLL locking time, 18- μs calibration time is achieved. Moreover, most parts of the calibration circuitries can be shared with the receiver chain, reducing the circuit complexity overhead.

A 3.3-MHz fast-response load-dependent-on/off-time buck-boost DC-DC converter with low-noise hybrid full-wave current sensor

Abstract A 3.3-MHz current mode control buck-boost DC-DC converter is proposed in this work. Composed of comparator control and load-dependent on/off time modulation technique, the converter can achieve a faster load transient response by reducing the delay from 2.7 μs to 1.5 μs during constant on/off time. Thus, the comparator can take effect faster. To fulfill a fixed frequency operation to reduce electromagnetic interference (EMI), a frequency controller locks the switching frequency to 3.3u202fMHz. Also, a hybrid full-wave current sensor is proposed to achieve current mode control. The proposed hybrid current sensor inherits good AC performance from a filter-based current sensor and good DC performance from a SenseFET-based one. As a result, state switching between high-side sensing and low-side sensing will not induce large spiking on the current sensor output. Moreover, the DC accuracy of current sensing will not be affected by the DC resistance (DCR) of the inductor.

Improved Nauta transconductor for wideband intermediate-frequency gm-C filter

An improved Nauta transconductor, with output resistance for differential-mode output signals insensitive to process and tuning voltage variations, is presented in this paper. Comparing with the classical Nauta transconductor, the proposed transconductor introduces 4 auxiliary inverters only. It can increase the differential-mode output resistance, and keep the common-mode output resistance nearly no changed at the same time. The proposed transconductor has been implemented in a 7th-order transconductance-C (gm-C) band-pass filter (BPF) in a standard 0.18-μm CMOS technology. The proposed filter has achieved a bandwidth of 20 MHz under a 15-MHz center frequency. Monte Carlo simulation results show that with the same tuning voltage range, the gain deviation of the filter with proposed transconductors is reduced 4.4 dB comparing with the counterpart based on classical Nauta transconductors, and the sensitivity of the quality (Q) factor of filter poles to tuning voltage is also significantly reduced. Measurement results show that the pass-band ripple of the proposed filter is reduced 1 dB, and the stop-band attenuation is reduced 8 dB at 30 MHz.

Cascoded flipped voltage follower based output-capacitorless low-dropout regulator for SoCs

A novel cascoded flipped voltage follower (CAFVF) based output-capacitorless low-dropout (LDO) regulator is proposed and implemented in 0.18-μm CMOS technology. With a cascode current source (CCS) embedded into the CAFVF structure, the proposed LDO regulator achieves 58.6-dB DC gain in heavy loading condition (100 mA), which is 44-dB for the conventional CAFVF counterpart under identical conditions. The cascode compensation technique is introduced to widen the loop bandwidth and reduce the minimal loading requirement. With a 5-pF compensation capacitor, the minimum load current to keep the proposed LDO regulator stable is reduced to 50 μA. In addition, the unity-gain frequency (UGF) is extended from 1.51 MHz to 2.36 MHz in 100-mA loading condition. Moreover, an accurate stability analysis without ignoring any channel resistance has been presented in this work. Simulation results show that the LDO regulator consumes an ultra-low quiescent current (Iq) of 14 μA for input voltage ranging from 1.2 V to 1.8 V, with a dropout voltage (Vdrop) of 200 mV.

A 3.5-A buck DC-DC regulator with wire drop compensation for remote-loading applications

Voltage drop introduced by long cable cannot be neglected any more in high-power remote-loading applications, e.g., power adaptor for the charger of modern smart phones or tablets. In this paper, self-adaptive wire drop compensation (WDC) schemes for DC-DC regulator have been proposed and discussed. A 3.5-A buck DC-DC regulator with the proposed WDC circuit has been implemented in 0.6μm CMOS technology. Simulation results show that the load regulation (0.004 V/A) is typically improved by 51 times than the circuit without WDC when load current changes from 0.5 A to 3 A.

A compact I/Q imbalance calibration technique for power-aware fully-integrated receiver without on-chip baseband processor

The in-phase and quadrature (I/Q) calibration has been typically implemented in DSP/MCU to reject image in receive chain. In this work, a compact, fully-integrated calibration technique is proposed without the need of baseband processors, which is very suitable for low-power low-cost wireless applications. By making use of the transmitter (TX) phase loop lock (PLL) in frequency duplex division (FDD) mode, a clean, compact calibration source is implemented with only 0.069mm2 extra area. The proposed calibration technique has been applied to an FDD transceiver in 0.13-μm CMOS technology. The measurements show that with the proposed calibration, a -60-dBc image rejection ratio (IRR), a minimum 1.7% error vector magnitude (EVM), and a 26-μs calibration time are achieved.1